[llvm] 5734a81 - [RISCV] Increase scalar integer divide latency for SiFive7.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-05-22T13:37:34-07:00
New Revision: 5734a81a5527dec3e63bebe842ac0bb9e2ff9025

URL: https://github.com/llvm/llvm-project/commit/5734a81a5527dec3e63bebe842ac0bb9e2ff9025
DIFF: https://github.com/llvm/llvm-project/commit/5734a81a5527dec3e63bebe842ac0bb9e2ff9025.diff

LOG: [RISCV] Increase scalar integer divide latency for SiFive7.

The scalar divider produces 1 bit per cycle so the worst case
latency is the input width plus a couple cycles.

Reviewed By: michaelmaitland

Differential Revision: https://reviews.llvm.org/D151139

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 2ddf3cc8224b..77bea1f90bb0 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -198,12 +198,12 @@ def : WriteRes<WriteIMul32, [SiFive7PipeB]>;
 
 // Integer division
 def : WriteRes<WriteIDiv, [SiFive7PipeB, SiFive7IDiv]> {
-  let Latency = 16;
-  let ResourceCycles = [1, 15];
+  let Latency = 66;
+  let ResourceCycles = [1, 65];
 }
 def : WriteRes<WriteIDiv32,  [SiFive7PipeB, SiFive7IDiv]> {
-  let Latency = 16;
-  let ResourceCycles = [1, 15];
+  let Latency = 34;
+  let ResourceCycles = [1, 33];
 }
 
 // Bitmanip