[PATCH] D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:321
+    auto Offset = MBBI->getOperand(2).getOffset();
+    assert(Offset == 0);
+    MBBI->getOperand(2).setOffset(Offset + 4);
----------------
This assert should be Offset %8 == 0 like it is in the store case.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:2401
 
+bool RISCVDAGToDAGISel::SelectAddrRegImmINX(SDValue Addr, SDValue &Base,
+                                            SDValue &Offset) {
----------------
Do not copy and paste the entire original function with only a small change. Add a boolean flag to the existing function and change only the behavior that needs to change.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149743/new/

https://reviews.llvm.org/D149743