[llvm] 83178d0 - [RISCV] Add missing zfh extensions to fixed vector load/store tests
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Mon May 22 09:34:11 PDT 2023
Author: Luke Lau
Date: 2023-05-22T17:33:59+01:00
New Revision: 83178d0a533bf55605a8009d7d40476f15c96c54
URL: https://github.com/llvm/llvm-project/commit/83178d0a533bf55605a8009d7d40476f15c96c54
DIFF: https://github.com/llvm/llvm-project/commit/83178d0a533bf55605a8009d7d40476f15c96c54.diff
LOG: [RISCV] Add missing zfh extensions to fixed vector load/store tests
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
index ec47b5f7b3dd6..94f189e857ed9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
define <5 x i8> @load_v5i8(ptr %p) {
; RV32-LABEL: load_v5i8:
@@ -123,29 +123,11 @@ define <6 x i16> @load_v6i16(ptr %p) {
}
define <6 x half> @load_v6f16(ptr %p) {
-; RV32-LABEL: load_v6f16:
-; RV32: # %bb.0:
-; RV32-NEXT: lw a2, 8(a1)
-; RV32-NEXT: lw a3, 4(a1)
-; RV32-NEXT: lw a1, 0(a1)
-; RV32-NEXT: sw a2, 8(a0)
-; RV32-NEXT: sw a3, 4(a0)
-; RV32-NEXT: sw a1, 0(a0)
-; RV32-NEXT: ret
-;
-; RV64-LABEL: load_v6f16:
-; RV64: # %bb.0:
-; RV64-NEXT: ld a2, 0(a1)
-; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV64-NEXT: ld a1, 8(a1)
-; RV64-NEXT: vslide1down.vx v8, v8, a2
-; RV64-NEXT: vslide1down.vx v8, v8, a1
-; RV64-NEXT: sd a2, 0(a0)
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT: vslidedown.vi v8, v8, 2
-; RV64-NEXT: addi a0, a0, 8
-; RV64-NEXT: vse32.v v8, (a0)
-; RV64-NEXT: ret
+; CHECK-LABEL: load_v6f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: ret
%x = load <6 x half>, ptr %p
ret <6 x half> %x
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
index 5c06e45e03cdb..f9290bab2bfb9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
define void @store_v5i8(ptr %p, <5 x i8> %v) {
; CHECK-LABEL: store_v5i8:
@@ -103,56 +103,16 @@ define void @store_v6i16(ptr %p, <6 x i16> %v) {
define void @store_v6f16(ptr %p, <6 x half> %v) {
; RV32-LABEL: store_v6f16:
; RV32: # %bb.0:
-; RV32-NEXT: lh a2, 20(a1)
-; RV32-NEXT: lhu a3, 16(a1)
-; RV32-NEXT: slli a2, a2, 16
-; RV32-NEXT: or a2, a3, a2
-; RV32-NEXT: lh a3, 12(a1)
-; RV32-NEXT: lhu a4, 8(a1)
-; RV32-NEXT: lh a5, 4(a1)
-; RV32-NEXT: lhu a1, 0(a1)
-; RV32-NEXT: slli a3, a3, 16
-; RV32-NEXT: or a3, a4, a3
-; RV32-NEXT: slli a5, a5, 16
-; RV32-NEXT: or a1, a1, a5
-; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vslide1down.vx v8, v8, a1
-; RV32-NEXT: vslide1down.vx v8, v8, a3
-; RV32-NEXT: vslide1down.vx v8, v8, a2
-; RV32-NEXT: vslidedown.vi v8, v8, 1
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: vslidedown.vi v9, v8, 2
; RV32-NEXT: addi a1, a0, 8
; RV32-NEXT: vse32.v v9, (a1)
-; RV32-NEXT: vslidedown.vi v8, v8, 1
-; RV32-NEXT: addi a0, a0, 4
-; RV32-NEXT: vse32.v v8, (a0)
+; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV32-NEXT: vse16.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: store_v6f16:
; RV64: # %bb.0:
-; RV64-NEXT: lhu a2, 16(a1)
-; RV64-NEXT: lh a3, 24(a1)
-; RV64-NEXT: slli a2, a2, 32
-; RV64-NEXT: lh a4, 8(a1)
-; RV64-NEXT: lhu a5, 0(a1)
-; RV64-NEXT: slli a3, a3, 48
-; RV64-NEXT: or a2, a3, a2
-; RV64-NEXT: slli a4, a4, 16
-; RV64-NEXT: or a4, a5, a4
-; RV64-NEXT: slli a4, a4, 32
-; RV64-NEXT: lh a3, 40(a1)
-; RV64-NEXT: lhu a1, 32(a1)
-; RV64-NEXT: srli a4, a4, 32
-; RV64-NEXT: or a2, a4, a2
-; RV64-NEXT: slli a3, a3, 16
-; RV64-NEXT: or a1, a1, a3
-; RV64-NEXT: slli a1, a1, 32
-; RV64-NEXT: srli a1, a1, 32
-; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV64-NEXT: vslide1down.vx v8, v8, a2
-; RV64-NEXT: vslide1down.vx v8, v8, a1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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