[llvm] 5d3412a - [InstCombine] Insert a bitcast to enable merging similar store insts
Anshil Gandhi via llvm-commits
llvm-commits at lists.llvm.org
Mon May 22 07:37:17 PDT 2023
Author: Anshil Gandhi
Date: 2023-05-22T07:36:45-07:00
New Revision: 5d3412a6d17bbd57160c252f513779f12ac44eb8
URL: https://github.com/llvm/llvm-project/commit/5d3412a6d17bbd57160c252f513779f12ac44eb8
DIFF: https://github.com/llvm/llvm-project/commit/5d3412a6d17bbd57160c252f513779f12ac44eb8.diff
LOG: [InstCombine] Insert a bitcast to enable merging similar store insts
Given two Store instructions with equivalent pointer operands,
they could be merged into their common successor basic block if
the value operand of one is bitcasted to match the type of the
other.
Differential Revision: https://reviews.llvm.org/D150900
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
index f62a8ca176843..c89dbe7750f1a 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
@@ -1611,6 +1611,17 @@ bool InstCombinerImpl::mergeStoreIntoSuccessor(StoreInst &SI) {
if (!OtherBr || BBI == OtherBB->begin())
return false;
+ auto OtherStoreIsMergeable = [&](StoreInst *OtherStore) -> bool {
+ if (!OtherStore ||
+ OtherStore->getPointerOperand() != SI.getPointerOperand())
+ return false;
+
+ auto *SIVTy = SI.getValueOperand()->getType();
+ auto *OSVTy = OtherStore->getValueOperand()->getType();
+ return CastInst::isBitOrNoopPointerCastable(OSVTy, SIVTy, DL) &&
+ SI.hasSameSpecialState(OtherStore);
+ };
+
// If the other block ends in an unconditional branch, check for the 'if then
// else' case. There is an instruction before the branch.
StoreInst *OtherStore = nullptr;
@@ -1626,8 +1637,7 @@ bool InstCombinerImpl::mergeStoreIntoSuccessor(StoreInst &SI) {
// If this isn't a store, isn't a store to the same location, or is not the
// right kind of store, bail out.
OtherStore = dyn_cast<StoreInst>(BBI);
- if (!OtherStore || OtherStore->getOperand(1) != SI.getOperand(1) ||
- !SI.isSameOperationAs(OtherStore))
+ if (!OtherStoreIsMergeable(OtherStore))
return false;
} else {
// Otherwise, the other block ended with a conditional branch. If one of the
@@ -1641,12 +1651,10 @@ bool InstCombinerImpl::mergeStoreIntoSuccessor(StoreInst &SI) {
// lives in OtherBB.
for (;; --BBI) {
// Check to see if we find the matching store.
- if ((OtherStore = dyn_cast<StoreInst>(BBI))) {
- if (OtherStore->getOperand(1) != SI.getOperand(1) ||
- !SI.isSameOperationAs(OtherStore))
- return false;
+ OtherStore = dyn_cast<StoreInst>(BBI);
+ if (OtherStoreIsMergeable(OtherStore))
break;
- }
+
// If we find something that may be using or overwriting the stored
// value, or if we run out of instructions, we can't do the transform.
if (BBI->mayReadFromMemory() || BBI->mayThrow() ||
@@ -1664,14 +1672,17 @@ bool InstCombinerImpl::mergeStoreIntoSuccessor(StoreInst &SI) {
}
// Insert a PHI node now if we need it.
- Value *MergedVal = OtherStore->getOperand(0);
+ Value *MergedVal = OtherStore->getValueOperand();
// The debug locations of the original instructions might
diff er. Merge them.
DebugLoc MergedLoc = DILocation::getMergedLocation(SI.getDebugLoc(),
OtherStore->getDebugLoc());
- if (MergedVal != SI.getOperand(0)) {
- PHINode *PN = PHINode::Create(MergedVal->getType(), 2, "storemerge");
- PN->addIncoming(SI.getOperand(0), SI.getParent());
- PN->addIncoming(OtherStore->getOperand(0), OtherBB);
+ if (MergedVal != SI.getValueOperand()) {
+ PHINode *PN =
+ PHINode::Create(SI.getValueOperand()->getType(), 2, "storemerge");
+ PN->addIncoming(SI.getValueOperand(), SI.getParent());
+ Builder.SetInsertPoint(OtherStore);
+ PN->addIncoming(Builder.CreateBitOrPointerCast(MergedVal, PN->getType()),
+ OtherBB);
MergedVal = InsertNewInstBefore(PN, DestBB->front());
PN->setDebugLoc(MergedLoc);
}
diff --git a/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll b/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll
index 35c3b11e1aafc..d70508117d1b8 100644
--- a/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll
+++ b/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll
@@ -71,3 +71,233 @@ bb10: ; preds = %bb
bb12: ; preds = %bb10, %bb9
ret void
}
+
+define half @
diff _types_same_width_merge(i1 %cond, half %a, i16 %b) {
+; CHECK-LABEL: @
diff _types_same_width_merge(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB0:%.*]], label [[BB1:%.*]]
+; CHECK: BB0:
+; CHECK-NEXT: br label [[SINK:%.*]]
+; CHECK: BB1:
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast i16 [[B:%.*]] to half
+; CHECK-NEXT: br label [[SINK]]
+; CHECK: sink:
+; CHECK-NEXT: [[STOREMERGE:%.*]] = phi half [ [[TMP0]], [[BB1]] ], [ [[A:%.*]], [[BB0]] ]
+; CHECK-NEXT: ret half [[STOREMERGE]]
+;
+entry:
+ %alloca = alloca half
+ br i1 %cond, label %BB0, label %BB1
+BB0:
+ store half %a, ptr %alloca
+ br label %sink
+BB1:
+ store i16 %b, ptr %alloca
+ br label %sink
+sink:
+ %val = load half, ptr %alloca
+ ret half %val
+}
+
+define i32 @
diff _types_
diff _width_no_merge(i1 %cond, i32 %a, i64 %b) {
+; CHECK-LABEL: @
diff _types_
diff _width_no_merge(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i64, align 8
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[A:%.*]], label [[B:%.*]]
+; CHECK: A:
+; CHECK-NEXT: store i32 [[A:%.*]], ptr [[ALLOCA]], align 8
+; CHECK-NEXT: br label [[SINK:%.*]]
+; CHECK: B:
+; CHECK-NEXT: store i64 [[B:%.*]], ptr [[ALLOCA]], align 8
+; CHECK-NEXT: br label [[SINK]]
+; CHECK: sink:
+; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ALLOCA]], align 8
+; CHECK-NEXT: ret i32 [[VAL]]
+;
+entry:
+ %alloca = alloca i64
+ br i1 %cond, label %A, label %B
+A:
+ store i32 %a, ptr %alloca
+ br label %sink
+B:
+ store i64 %b, ptr %alloca
+ br label %sink
+sink:
+ %val = load i32, ptr %alloca
+ ret i32 %val
+}
+
+define <4 x i32> @vec_no_merge(i1 %cond, <2 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @vec_no_merge(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i64, align 16
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[A:%.*]], label [[B:%.*]]
+; CHECK: A:
+; CHECK-NEXT: store <2 x i32> [[A:%.*]], ptr [[ALLOCA]], align 16
+; CHECK-NEXT: br label [[SINK:%.*]]
+; CHECK: B:
+; CHECK-NEXT: store <4 x i32> [[B:%.*]], ptr [[ALLOCA]], align 16
+; CHECK-NEXT: br label [[SINK]]
+; CHECK: sink:
+; CHECK-NEXT: [[VAL:%.*]] = load <4 x i32>, ptr [[ALLOCA]], align 16
+; CHECK-NEXT: ret <4 x i32> [[VAL]]
+;
+entry:
+ %alloca = alloca i64
+ br i1 %cond, label %A, label %B
+A:
+ store <2 x i32> %a, ptr %alloca
+ br label %sink
+B:
+ store <4 x i32> %b, ptr %alloca
+ br label %sink
+sink:
+ %val = load <4 x i32>, ptr %alloca
+ ret <4 x i32> %val
+}
+
+%struct.half = type { half };
+
+define %struct.half @one_elem_struct_merge(i1 %cond, %struct.half %a, half %b) {
+; CHECK-LABEL: @one_elem_struct_merge(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB0:%.*]], label [[BB1:%.*]]
+; CHECK: BB0:
+; CHECK-NEXT: [[TMP0:%.*]] = extractvalue [[STRUCT_HALF:%.*]] [[A:%.*]], 0
+; CHECK-NEXT: br label [[SINK:%.*]]
+; CHECK: BB1:
+; CHECK-NEXT: br label [[SINK]]
+; CHECK: sink:
+; CHECK-NEXT: [[STOREMERGE:%.*]] = phi half [ [[TMP0]], [[BB0]] ], [ [[B:%.*]], [[BB1]] ]
+; CHECK-NEXT: [[VAL1:%.*]] = insertvalue [[STRUCT_HALF]] poison, half [[STOREMERGE]], 0
+; CHECK-NEXT: ret [[STRUCT_HALF]] [[VAL1]]
+;
+entry:
+ %alloca = alloca i64
+ br i1 %cond, label %BB0, label %BB1
+BB0:
+ store %struct.half %a, ptr %alloca
+ br label %sink
+BB1:
+ store half %b, ptr %alloca
+ br label %sink
+sink:
+ %val = load %struct.half, ptr %alloca
+ ret %struct.half %val
+}
+
+%struct.tup = type { half, i32 };
+
+define %struct.tup @multi_elem_struct_no_merge(i1 %cond, %struct.tup %a, half %b) {
+; CHECK-LABEL: @multi_elem_struct_no_merge(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i64, align 8
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[A:%.*]], label [[B:%.*]]
+; CHECK: A:
+; CHECK-NEXT: store [[STRUCT_TUP:%.*]] [[A:%.*]], ptr [[ALLOCA]], align 8
+; CHECK-NEXT: br label [[SINK:%.*]]
+; CHECK: B:
+; CHECK-NEXT: store half [[B:%.*]], ptr [[ALLOCA]], align 8
+; CHECK-NEXT: br label [[SINK]]
+; CHECK: sink:
+; CHECK-NEXT: [[VAL:%.*]] = load [[STRUCT_TUP]], ptr [[ALLOCA]], align 8
+; CHECK-NEXT: ret [[STRUCT_TUP]] [[VAL]]
+;
+entry:
+ %alloca = alloca i64
+ br i1 %cond, label %A, label %B
+A:
+ store %struct.tup %a, ptr %alloca
+ br label %sink
+B:
+ store half %b, ptr %alloca
+ br label %sink
+sink:
+ %val = load %struct.tup, ptr %alloca
+ ret %struct.tup %val
+}
+
+define i16 @same_types_
diff _align_no_merge(i1 %cond, i16 %a, i16 %b) {
+; CHECK-LABEL: @same_types_
diff _align_no_merge(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i16, align 4
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB0:%.*]], label [[BB1:%.*]]
+; CHECK: BB0:
+; CHECK-NEXT: store i16 [[A:%.*]], ptr [[ALLOCA]], align 8
+; CHECK-NEXT: br label [[SINK:%.*]]
+; CHECK: BB1:
+; CHECK-NEXT: store i16 [[B:%.*]], ptr [[ALLOCA]], align 4
+; CHECK-NEXT: br label [[SINK]]
+; CHECK: sink:
+; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr [[ALLOCA]], align 4
+; CHECK-NEXT: ret i16 [[VAL]]
+;
+entry:
+ %alloca = alloca i16, align 4
+ br i1 %cond, label %BB0, label %BB1
+BB0:
+ store i16 %a, ptr %alloca, align 8
+ br label %sink
+BB1:
+ store i16 %b, ptr %alloca, align 4
+ br label %sink
+sink:
+ %val = load i16, ptr %alloca
+ ret i16 %val
+}
+
+define i64 @ptrtoint_merge(i1 %cond, i64 %a, ptr %b) {
+; CHECK-LABEL: @ptrtoint_merge(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB0:%.*]], label [[BB1:%.*]]
+; CHECK: BB0:
+; CHECK-NEXT: br label [[SINK:%.*]]
+; CHECK: BB1:
+; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[B:%.*]] to i64
+; CHECK-NEXT: br label [[SINK]]
+; CHECK: sink:
+; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i64 [ [[A:%.*]], [[BB0]] ], [ [[TMP0]], [[BB1]] ]
+; CHECK-NEXT: ret i64 [[STOREMERGE]]
+;
+entry:
+ %alloca = alloca ptr
+ br i1 %cond, label %BB0, label %BB1
+BB0:
+ store i64 %a, ptr %alloca
+ br label %sink
+BB1:
+ store ptr %b, ptr %alloca
+ br label %sink
+sink:
+ %val = load i64, ptr %alloca
+ ret i64 %val
+}
+
+define ptr @inttoptr_merge(i1 %cond, i64 %a, ptr %b) {
+; CHECK-LABEL: define ptr @inttoptr_merge
+; CHECK-SAME: (i1 [[COND:%.*]], i64 [[A:%.*]], ptr [[B:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[COND]], label [[BB0:%.*]], label [[BB1:%.*]]
+; CHECK: BB0:
+; CHECK-NEXT: [[TMP0:%.*]] = inttoptr i64 [[A]] to ptr
+; CHECK-NEXT: br label [[SINK:%.*]]
+; CHECK: BB1:
+; CHECK-NEXT: br label [[SINK]]
+; CHECK: sink:
+; CHECK-NEXT: [[STOREMERGE:%.*]] = phi ptr [ [[B]], [[BB1]] ], [ [[TMP0]], [[BB0]] ]
+; CHECK-NEXT: ret ptr [[STOREMERGE]]
+;
+entry:
+ %alloca = alloca ptr
+ br i1 %cond, label %BB0, label %BB1
+BB0:
+ store i64 %a, ptr %alloca, align 8
+ br label %sink
+BB1:
+ store ptr %b, ptr %alloca, align 8
+ br label %sink
+sink:
+ %val = load ptr, ptr %alloca
+ ret ptr %val
+}
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