[llvm] ffa32cd - [RISCV] Disable constant hoiting for multiply by a power of 2.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat May 20 19:21:04 PDT 2023
Author: Craig Topper
Date: 2023-05-20T19:20:49-07:00
New Revision: ffa32cd11e5e0f42acd3540dd4313283cd0fc010
URL: https://github.com/llvm/llvm-project/commit/ffa32cd11e5e0f42acd3540dd4313283cd0fc010
DIFF: https://github.com/llvm/llvm-project/commit/ffa32cd11e5e0f42acd3540dd4313283cd0fc010.diff
LOG: [RISCV] Disable constant hoiting for multiply by a power of 2.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 34626e249e7b..528c2072be9d 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -142,8 +142,8 @@ InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
Takes12BitImm = true;
break;
case Instruction::Mul:
- // Negated power of 2 is a shift and a negate.
- if (Imm.isNegatedPowerOf2())
+ // Power of 2 is a shift. Negated power of 2 is a shift and a negate.
+ if (Imm.isPowerOf2() || Imm.isNegatedPowerOf2())
return TTI::TCC_Free;
// FIXME: There is no MULI instruction.
Takes12BitImm = true;
diff --git a/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll b/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
index 97aa19e68f91..4cf028d05780 100644
--- a/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
+++ b/llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
@@ -122,3 +122,13 @@ define i64 @test13(i64 %a) nounwind "target-features"="+zbs" {
%2 = and i64 %1, -281474976710657 ; ~(1 << 48)
ret i64 %2
}
+
+; Check that we don't hoist mul by a power of 2.
+define i64 @test14(i64 %a) nounwind {
+; CHECK-LABEL: test14
+; CHECK: mul i64 %a, 2048
+ %1 = mul i64 %a, 2048
+ %2 = mul i64 %1, 2048
+ ret i64 %2
+}
+
More information about the llvm-commits
mailing list