[llvm] 2e6bfa8 - [RISCV] Update pr58511.ll to not use mul by constant that can be converted to shift.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-05-20T19:08:05-07:00
New Revision: 2e6bfa8ed08c94e2edbe673379c90012efc95abb

URL: https://github.com/llvm/llvm-project/commit/2e6bfa8ed08c94e2edbe673379c90012efc95abb
DIFF: https://github.com/llvm/llvm-project/commit/2e6bfa8ed08c94e2edbe673379c90012efc95abb.diff

LOG: [RISCV] Update pr58511.ll to not use mul by constant that can be converted to shift.

Normally a mul by a power 2 will be converted to shift by InstCombine.
Hoping this will make D127115 not affect this test so much.

I've verified the change still fails with the original DAGCombiner
bug.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/pr58511.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/pr58511.ll b/llvm/test/CodeGen/RISCV/pr58511.ll
index 8b67370abfe4..628090364f84 100644
--- a/llvm/test/CodeGen/RISCV/pr58511.ll
+++ b/llvm/test/CodeGen/RISCV/pr58511.ll
@@ -1,23 +1,21 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s
 
 define i32 @f(i1 %0, i32 %1, ptr %2) {
 ; CHECK-LABEL: f:
 ; CHECK:       # %bb.0: # %BB
-; CHECK-NEXT:    slli a3, a1, 11
-; CHECK-NEXT:    slli a1, a1, 12
-; CHECK-NEXT:    subw a1, a1, a3
+; CHECK-NEXT:    lui a3, 4097
+; CHECK-NEXT:    addiw a3, a3, -2047
+; CHECK-NEXT:    mul a1, a1, a3
 ; CHECK-NEXT:    slli a0, a0, 63
 ; CHECK-NEXT:    srai a0, a0, 63
-; CHECK-NEXT:    li a3, 1
-; CHECK-NEXT:    slli a3, a3, 11
 ; CHECK-NEXT:    or a0, a0, a3
 ; CHECK-NEXT:    sw a1, 0(a2)
 ; CHECK-NEXT:    ret
 BB:
   %I = select i1 %0, i32 -1, i32 0
-  %I1 = mul i32 %1, 2048
-  %I2 = or i32 2048, %I
+  %I1 = mul i32 %1, 16779265
+  %I2 = or i32 16779265, %I
   store i32 %I1, ptr %2
   ret i32 %I2
 }
@@ -25,20 +23,18 @@ BB:
 define i32 @g(i1 %0, i32 %1, ptr %2) {
 ; CHECK-LABEL: g:
 ; CHECK:       # %bb.0: # %BB
-; CHECK-NEXT:    slli a3, a1, 11
-; CHECK-NEXT:    slli a1, a1, 12
-; CHECK-NEXT:    subw a1, a1, a3
+; CHECK-NEXT:    lui a3, 4097
+; CHECK-NEXT:    addiw a3, a3, -2047
+; CHECK-NEXT:    mul a1, a1, a3
 ; CHECK-NEXT:    andi a0, a0, 1
 ; CHECK-NEXT:    addi a0, a0, -1
-; CHECK-NEXT:    li a3, 1
-; CHECK-NEXT:    slli a3, a3, 11
 ; CHECK-NEXT:    or a0, a0, a3
 ; CHECK-NEXT:    sw a1, 0(a2)
 ; CHECK-NEXT:    ret
 BB:
   %I = select i1 %0, i32 0, i32 -1
-  %I1 = mul i32 %1, 2048
-  %I2 = or i32 2048, %I
+  %I1 = mul i32 %1, 16779265
+  %I2 = or i32 16779265, %I
   store i32 %I1, ptr %2
   ret i32 %I2
 }
@@ -46,17 +42,18 @@ BB:
 define i32 @h(i1 %0, i32 %1, ptr %2) {
 ; CHECK-LABEL: h:
 ; CHECK:       # %bb.0: # %BB
-; CHECK-NEXT:    slli a3, a1, 11
-; CHECK-NEXT:    slli a1, a1, 12
-; CHECK-NEXT:    subw a1, a1, a3
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    slli a0, a0, 11
+; CHECK-NEXT:    lui a3, 4097
+; CHECK-NEXT:    addiw a3, a3, -2047
+; CHECK-NEXT:    mul a1, a1, a3
+; CHECK-NEXT:    slli a0, a0, 63
+; CHECK-NEXT:    srai a0, a0, 63
+; CHECK-NEXT:    and a0, a0, a3
 ; CHECK-NEXT:    sw a1, 0(a2)
 ; CHECK-NEXT:    ret
 BB:
   %I = select i1 %0, i32 -1, i32 0
-  %I1 = mul i32 %1, 2048
-  %I2 = and i32 2048, %I
+  %I1 = mul i32 %1, 16779265
+  %I2 = and i32 16779265, %I
   store i32 %I1, ptr %2
   ret i32 %I2
 }
@@ -65,19 +62,17 @@ define i32 @i(i1 %0, i32 %1, ptr %2) {
 ; CHECK-LABEL: i:
 ; CHECK:       # %bb.0: # %BB
 ; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    slli a3, a1, 11
-; CHECK-NEXT:    slli a1, a1, 12
-; CHECK-NEXT:    subw a1, a1, a3
+; CHECK-NEXT:    lui a3, 4097
+; CHECK-NEXT:    addiw a3, a3, -2047
+; CHECK-NEXT:    mul a1, a1, a3
 ; CHECK-NEXT:    addi a0, a0, -1
-; CHECK-NEXT:    li a3, 1
-; CHECK-NEXT:    slli a3, a3, 11
 ; CHECK-NEXT:    and a0, a0, a3
 ; CHECK-NEXT:    sw a1, 0(a2)
 ; CHECK-NEXT:    ret
 BB:
   %I = select i1 %0, i32 0, i32 -1
-  %I1 = mul i32 %1, 2048
-  %I2 = and i32 2048, %I
+  %I1 = mul i32 %1, 16779265
+  %I2 = and i32 16779265, %I
   store i32 %I1, ptr %2
   ret i32 %I2
 }