[PATCH] D150956: [AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for ld1/ldnt1/st1/stnt1

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:3842
+                   (aarch64svcount PPR:$PNg), GPR64:$base),
+            (RegImmInst (REG_SEQUENCE ZPR2, Ty:$vec0, zsub0, Ty:$vec1, zsub1),
+                         PPR:$PNg, GPR64:$base, (i64 0))>;
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CarolineConcatto wrote:
> Should this be ZPR2Mul2 same for store_pn_x4 I think it should ZPR4Mul4, because the multivectors are all mul_r?
It should, although oddly it was doing the right thing, probably because of the register class defined for the instruction.


Repository:
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  https://reviews.llvm.org/D150956/new/

https://reviews.llvm.org/D150956