[PATCH] D150956: [AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for ld1/ldnt1/st1/stnt1

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen updated this revision to Diff 523792.
sdesmalen added a comment.

Changed register class to ZPR2Mul2, ZPR4Mul4.
Udated the store tests to take a `unused` argument, which forces all tests to copy input registers to tuple that is a multiple of 2 or 4.
Removed the explicit tests for these cases, as those are now redundant.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150956/new/

https://reviews.llvm.org/D150956

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve2p1-intrinsics-loads.ll
  llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll

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