[PATCH] D150949: [X86] Remove patterns for ADD/AND/OR/SUB/XOR/CMP with immediate 8 and optimize during MC lowering, NFCI

[Kan Shengchen via Phabricator via llvm-commits]

This revision was not accepted when it landed; it landed in state "Needs Review".
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5586bc539acb: [X86] Remove patterns for ADD/AND/OR/SUB/XOR/CMP with immediate 8 and optimize… (authored by skan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150949/new/

https://reviews.llvm.org/D150949

Files:
  llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h
  llvm/lib/Target/X86/X86CallFrameOptimization.cpp
  llvm/lib/Target/X86/X86DynAllocaExpander.cpp
  llvm/lib/Target/X86/X86FastISel.cpp
  llvm/lib/Target/X86/X86FixupLEAs.cpp
  llvm/lib/Target/X86/X86FrameLowering.cpp
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86InstrAVX512.td
  llvm/lib/Target/X86/X86InstrArithmetic.td
  llvm/lib/Target/X86/X86InstrCompiler.td
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstructionSelector.cpp
  llvm/lib/Target/X86/X86MCInstLower.cpp
  llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir
  llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll
  llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir
  llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir
  llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
  llvm/test/CodeGen/X86/GlobalISel/select-ext.mir
  llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir
  llvm/test/CodeGen/X86/avxvnni-combine.ll
  llvm/test/CodeGen/X86/cfi-xmm.ll
  llvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll
  llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir
  llvm/test/CodeGen/X86/leaFixup32.mir
  llvm/test/CodeGen/X86/leaFixup64.mir
  llvm/test/CodeGen/X86/limit-split-cost.mir
  llvm/test/CodeGen/X86/machinesink-debug-inv-0.mir
  llvm/test/CodeGen/X86/optimize-compare.mir
  llvm/test/CodeGen/X86/peephole-fold-testrr.mir
  llvm/test/CodeGen/X86/pr46827.ll
  llvm/test/CodeGen/X86/push-cfi.ll
  llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
  llvm/test/CodeGen/X86/switch-bit-test-unreachable-default.ll
  llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll
  llvm/test/CodeGen/X86/tail-call-conditional.mir
  llvm/test/CodeGen/X86/tail-merge-after-mbp.mir
  llvm/test/CodeGen/X86/throws-cfi-fp.ll
  llvm/test/CodeGen/X86/twoaddr-dbg-value.mir
  llvm/test/CodeGen/X86/update-terminator-debugloc.ll
  llvm/test/CodeGen/X86/vecloadextract.ll
  llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
  llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir
  llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir
  llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir
  llvm/test/DebugInfo/MIR/X86/empty-inline.mir
  llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir
  llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir
  llvm/test/DebugInfo/MIR/X86/machinesink-subreg.mir
  llvm/test/DebugInfo/MIR/X86/machinesink.mir
  llvm/test/DebugInfo/MIR/X86/merge-inline-loc4.mir
  llvm/test/DebugInfo/MIR/X86/mlicm-hoist-post-regalloc.mir
  llvm/test/DebugInfo/X86/debug-loc-asan.mir
  llvm/test/DebugInfo/X86/debug-loc-offset.mir
  llvm/test/DebugInfo/X86/location-range.mir
  llvm/test/DebugInfo/X86/machinecse-wrongdebug-hoist.ll
  llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll
  llvm/test/DebugInfo/assignment-tracking/X86/lower-to-value.ll
  llvm/test/TableGen/x86-fold-tables.inc
  llvm/test/Transforms/SampleProfile/pseudo-probe-twoaddr.ll
  llvm/utils/TableGen/X86ManualFoldTables.def

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