[PATCH] D149383: [SelectionDAG][WIP] Add support for evaluating SetCC based on knownbits

Fri May 19 01:40:55 PDT 2023

foad added inline comments.

================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:4288-4289
+
+      // We aren't able to constant fold with known bits but can either 1) make
+      // conditions stronger (i.e ule -> ult) or 2) simplify with
+      // isKnownNeverZero if RHS is zero.
----------------
goldstein.w.n wrote:
> foad wrote:
> > Just curious: does "strengthening" conditions like this actually generate better code? Is it something we do elsewhere in the compiler?
> No worse in fact. This was really motivated by wanting to improve the knownbits analysis in selectiondag but having no good way to test it.
> 
> I think at the moment, since we don't have the infrastructure to fold basic blocks when `icmp; br` conditions are known `true/false` we end up with regressions.
> 
> Not sure exactly where this is going to go unless we add that infrastructure.
You're adding code to the compiler to change these setcc conditions, but not actually make anything better? I do not think that is a good idea.

================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:4302
+        if (!Res && KnownRHS.isZero() && DAG.isKnownNeverZero(N0))
+          Res = false;
+        break;
----------------
RKSimon wrote:
> I'm not sure this is always false?
It's confusing but I think it's correct. From this point onwards, `Res` represents whether LHS and RHS are //equal//, irrespective of `Cond`.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149383/new/

https://reviews.llvm.org/D149383