[PATCH] D150855: MachineCombiner: consider all uses in getLatency()
Ramkumar Ramachandra via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 18 03:32:04 PDT 2023
artagnon created this revision.
artagnon added reviewers: spatel, dexonsmith, asi-sc.
Herald added subscribers: StephenFan, hiraditya.
Herald added a project: All.
artagnon requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
getLatency() was considering only the first use when computing operand
latency. Fix this.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D150855
Files:
llvm/lib/CodeGen/MachineCombiner.cpp
Index: llvm/lib/CodeGen/MachineCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/MachineCombiner.cpp
+++ llvm/lib/CodeGen/MachineCombiner.cpp
@@ -217,12 +217,10 @@
// are tracked in the InstrIdxForVirtReg map depth is looked up in InstrDepth
for (auto *InstrPtr : InsInstrs) { // for each Use
unsigned IDepth = 0;
- for (const MachineOperand &MO : InstrPtr->operands()) {
+ for (const MachineOperand &MO : InstrPtr->uses()) {
// Check for virtual register operand.
if (!(MO.isReg() && MO.getReg().isVirtual()))
continue;
- if (!MO.isUse())
- continue;
unsigned DepthOp = 0;
unsigned LatencyOp = 0;
DenseMap<unsigned, unsigned>::iterator II =
@@ -272,27 +270,21 @@
// Check each definition in NewRoot and compute the latency
unsigned NewRootLatency = 0;
- for (const MachineOperand &MO : NewRoot->operands()) {
+ for (const MachineOperand &MO : NewRoot->defs()) {
// Check for virtual register operand.
if (!(MO.isReg() && MO.getReg().isVirtual()))
continue;
- if (!MO.isDef())
- continue;
- // Get the first instruction that uses MO
- MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(MO.getReg());
- RI++;
- if (RI == MRI->reg_end())
- continue;
- MachineInstr *UseMO = RI->getParent();
- unsigned LatencyOp = 0;
- if (UseMO && BlockTrace.isDepInTrace(*Root, *UseMO)) {
- LatencyOp = TSchedModel.computeOperandLatency(
- NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), UseMO,
- UseMO->findRegisterUseOperandIdx(MO.getReg()));
- } else {
- LatencyOp = TSchedModel.computeInstrLatency(NewRoot);
+ for (MachineInstr &UseInstr : MRI->use_instructions(MO.getReg())) {
+ unsigned LatencyOp = 0;
+ if (BlockTrace.isDepInTrace(*Root, UseInstr)) {
+ LatencyOp = TSchedModel.computeOperandLatency(
+ NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), &UseInstr,
+ UseInstr.findRegisterUseOperandIdx(MO.getReg()));
+ } else {
+ LatencyOp = TSchedModel.computeInstrLatency(NewRoot);
+ }
+ NewRootLatency = std::max(NewRootLatency, LatencyOp);
}
- NewRootLatency = std::max(NewRootLatency, LatencyOp);
}
return NewRootLatency;
}
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