[PATCH] D150717: [RISCV] Use scalar stores for splats of zero to memory up to XLen

Alex Bradbury via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 17 04:14:44 PDT 2023

asb added inline comments.

Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:12189
+      auto NewVT = MVT::getIntegerVT(MemVT.getSizeInBits());
+      if (allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(),
+                                         NewVT, *Store->getMemOperand())) {
luke wrote:
> Do we want to check if the memory access is fast? Currently we always report unaligned scalar accesses as slow, but that sounds like it's at odds with this combine
> ```
> bool RISCVTargetLowering::allowsMisalignedMemoryAccesses(
>     EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
>     unsigned *Fast) const {
>   if (!VT.isVector()) {
>     if (Fast)
>       *Fast = 0;
>     return Subtarget.enableUnalignedScalarMem();
>   }
> ```
Luke and I chatted about this earlier today, and the specific case would be where a vector access that is aligned according to the natural alignment of its elements is converted to a wider scalar access that is misaligned. Though now reminding myself of the how +unaligned-scalar-mem is used (https://reviews.llvm.org/D126085), this is probably not a concern, as it's only enabled if unaligned scalar mem is performant enough to be worth using.



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