[llvm] 4c6ae6e - [RISCV][NFC] Remove LMUL from vmv.s.x and vmv.x.s scheduler classes
Nitin John Raj via llvm-commits
llvm-commits at lists.llvm.org
Wed May 17 03:55:13 PDT 2023
Author: Nitin John Raj
Date: 2023-05-17T03:53:07-07:00
New Revision: 4c6ae6e0aa39e7d5e08b437f085dc6ae447dba83
URL: https://github.com/llvm/llvm-project/commit/4c6ae6e0aa39e7d5e08b437f085dc6ae447dba83
DIFF: https://github.com/llvm/llvm-project/commit/4c6ae6e0aa39e7d5e08b437f085dc6ae447dba83.diff
LOG: [RISCV][NFC] Remove LMUL from vmv.s.x and vmv.x.s scheduler classes
These instructions don't read or write register groups. We only pretend they do in intrinsics and pseudoinstructions.
Differential Revision: https://reviews.llvm.org/D150238
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
llvm/lib/Target/RISCV/RISCVScheduleV.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 1165672812ea..c3dc66fc7b61 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1615,12 +1615,11 @@ def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd),
let vm = 1, RVVConstraint = NoConstraint in {
def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
(ins VR:$vs2), "vmv.x.s", "$vd, $vs2">,
- Sched<[WriteVIMovVX_WorstCase, ReadVIMovVX_WorstCase]>;
+ Sched<[WriteVIMovVX, ReadVIMovVX]>;
let Constraints = "$vd = $vd_wb" in
def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VR:$vd_wb),
(ins VR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">,
- Sched<[WriteVIMovXV_WorstCase, ReadVIMovXV_WorstCase,
- ReadVIMovXX_WorstCase]>;
+ Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>;
}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
@@ -1634,12 +1633,11 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1,
// Floating-Point Scalar Move Instructions
def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd),
(ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">,
- Sched<[WriteVFMovVF_WorstCase, ReadVFMovVF_WorstCase]>;
+ Sched<[WriteVFMovVF, ReadVFMovVF]>;
let Constraints = "$vd = $vd_wb" in
def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VR:$vd_wb),
(ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">,
- Sched<[WriteVFMovFV_WorstCase, ReadVFMovFV_WorstCase,
- ReadVFMovFX_WorstCase]>;
+ Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index c797f9831dc3..85046f1b40a3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -6178,16 +6178,11 @@ let Predicates = [HasVInstructions] in {
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
foreach m = MxList in {
defvar mx = m.MX;
- defvar WriteVIMovVX_MX = !cast<SchedWrite>("WriteVIMovVX_" # mx);
- defvar WriteVIMovXV_MX = !cast<SchedWrite>("WriteVIMovXV_" # mx);
- defvar ReadVIMovVX_MX = !cast<SchedRead>("ReadVIMovVX_" # mx);
- defvar ReadVIMovXV_MX = !cast<SchedRead>("ReadVIMovXV_" # mx);
- defvar ReadVIMovXX_MX = !cast<SchedRead>("ReadVIMovXX_" # mx);
let VLMul = m.value in {
let HasSEWOp = 1, BaseInstr = VMV_X_S in
def PseudoVMV_X_S # "_" # mx:
Pseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, ixlenimm:$sew), []>,
- Sched<[WriteVIMovVX_MX, ReadVIMovVX_MX]>,
+ Sched<[WriteVIMovVX, ReadVIMovVX]>,
RISCVVPseudo;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X,
Constraints = "$rd = $rs1" in
@@ -6195,7 +6190,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
(ins m.vrclass:$rs1, GPR:$rs2,
AVL:$vl, ixlenimm:$sew),
[]>,
- Sched<[WriteVIMovXV_MX, ReadVIMovXV_MX, ReadVIMovXX_MX]>,
+ Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>,
RISCVVPseudo;
}
}
@@ -6211,17 +6206,12 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
foreach f = FPList in {
foreach m = f.MxList in {
defvar mx = m.MX;
- defvar WriteVFMovVF_MX = !cast<SchedWrite>("WriteVFMovVF_" # mx);
- defvar WriteVFMovFV_MX = !cast<SchedWrite>("WriteVFMovFV_" # mx);
- defvar ReadVFMovVF_MX = !cast<SchedRead>("ReadVFMovVF_" # mx);
- defvar ReadVFMovFV_MX = !cast<SchedRead>("ReadVFMovFV_" # mx);
- defvar ReadVFMovFX_MX = !cast<SchedRead>("ReadVFMovFX_" # mx);
let VLMul = m.value in {
let HasSEWOp = 1, BaseInstr = VFMV_F_S in
def "PseudoVFMV_" # f.FX # "_S_" # mx :
Pseudo<(outs f.fprclass:$rd),
(ins m.vrclass:$rs2, ixlenimm:$sew), []>,
- Sched<[WriteVFMovVF_MX, ReadVFMovVF_MX]>,
+ Sched<[WriteVFMovVF, ReadVFMovVF]>,
RISCVVPseudo;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F,
Constraints = "$rd = $rs1" in
@@ -6230,7 +6220,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
(ins m.vrclass:$rs1, f.fprclass:$rs2,
AVL:$vl, ixlenimm:$sew),
[]>,
- Sched<[WriteVFMovFV_MX, ReadVFMovFV_MX, ReadVFMovFX_MX]>,
+ Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>,
RISCVVPseudo;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 5404d5d13208..dc833d0df755 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -641,14 +641,16 @@ foreach mx = SchedMxList in {
}
// 16. Vector Permutation Instructions
+let Latency = 8, ResourceCycles = [1] in {
+ def : WriteRes<WriteVIMovVX, [SiFive7VA]>;
+ def : WriteRes<WriteVIMovXV, [SiFive7VA]>;
+ def : WriteRes<WriteVFMovVF, [SiFive7VA]>;
+ def : WriteRes<WriteVFMovFV, [SiFive7VA]>;
+}
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 8, ResourceCycles = [Cycles] in {
- defm "" : LMULWriteResMX<"WriteVIMovVX", [SiFive7VA], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMovXV", [SiFive7VA], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFMovVF", [SiFive7VA], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFMovFV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFive7VA], mx, IsWorstCase>;
}
@@ -929,12 +931,12 @@ defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
// 17. Vector Permutation Instructions
-defm "" : LMULReadAdvance<"ReadVIMovVX", 0>;
-defm "" : LMULReadAdvance<"ReadVIMovXV", 0>;
-defm "" : LMULReadAdvance<"ReadVIMovXX", 0>;
-defm "" : LMULReadAdvance<"ReadVFMovVF", 0>;
-defm "" : LMULReadAdvance<"ReadVFMovFV", 0>;
-defm "" : LMULReadAdvance<"ReadVFMovFX", 0>;
+def : ReadAdvance<ReadVIMovVX, 0>;
+def : ReadAdvance<ReadVIMovXV, 0>;
+def : ReadAdvance<ReadVIMovXX, 0>;
+def : ReadAdvance<ReadVFMovVF, 0>;
+def : ReadAdvance<ReadVFMovFV, 0>;
+def : ReadAdvance<ReadVFMovFX, 0>;
defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index 071e1a79e386..b6ab10454cfd 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -417,11 +417,11 @@ defm "" : LMULSchedWrites<"WriteVMIdxV">;
// 16. Vector Permutation Instructions
// 16.1. Integer Scalar Move Instructions
-defm "" : LMULSchedWrites<"WriteVIMovVX">;
-defm "" : LMULSchedWrites<"WriteVIMovXV">;
+def WriteVIMovVX : SchedWrite;
+def WriteVIMovXV : SchedWrite;
// 16.2. Floating-Point Scalar Move Instructions
-defm "" : LMULSchedWrites<"WriteVFMovVF">;
-defm "" : LMULSchedWrites<"WriteVFMovFV">;
+def WriteVFMovVF : SchedWrite;
+def WriteVFMovFV : SchedWrite;
// 16.3. Vector Slide Instructions
defm "" : LMULSchedWrites<"WriteVISlideX">;
defm "" : LMULSchedWrites<"WriteVISlideI">;
@@ -637,13 +637,13 @@ defm "" : LMULSchedReads<"ReadVMIotV">;
// 16. Vector Permutation Instructions
// 16.1. Integer Scalar Move Instructions
-defm "" : LMULSchedReads<"ReadVIMovVX">;
-defm "" : LMULSchedReads<"ReadVIMovXV">;
-defm "" : LMULSchedReads<"ReadVIMovXX">;
+def ReadVIMovVX : SchedRead;
+def ReadVIMovXV : SchedRead;
+def ReadVIMovXX : SchedRead;
// 16.2. Floating-Point Scalar Move Instructions
-defm "" : LMULSchedReads<"ReadVFMovVF">;
-defm "" : LMULSchedReads<"ReadVFMovFV">;
-defm "" : LMULSchedReads<"ReadVFMovFX">;
+def ReadVFMovVF : SchedRead;
+def ReadVFMovFV : SchedRead;
+def ReadVFMovFX : SchedRead;
// 16.3. Vector Slide Instructions
defm "" : LMULSchedReads<"ReadVISlideV">;
defm "" : LMULSchedReads<"ReadVISlideX">;
@@ -837,10 +837,10 @@ defm "" : LMULWriteRes<"WriteVMIotV", []>;
defm "" : LMULWriteRes<"WriteVMIdxV", []>;
// 16. Vector Permutation Instructions
-defm "" : LMULWriteRes<"WriteVIMovVX", []>;
-defm "" : LMULWriteRes<"WriteVIMovXV", []>;
-defm "" : LMULWriteRes<"WriteVFMovVF", []>;
-defm "" : LMULWriteRes<"WriteVFMovFV", []>;
+def : WriteRes<WriteVIMovVX, []>;
+def : WriteRes<WriteVIMovXV, []>;
+def : WriteRes<WriteVFMovVF, []>;
+def : WriteRes<WriteVFMovFV, []>;
defm "" : LMULWriteRes<"WriteVISlideX", []>;
defm "" : LMULWriteRes<"WriteVISlideI", []>;
defm "" : LMULWriteRes<"WriteVISlide1X", []>;
@@ -993,12 +993,12 @@ defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
// 16. Vector Permutation Instructions
-defm "" : LMULReadAdvance<"ReadVIMovVX", 0>;
-defm "" : LMULReadAdvance<"ReadVIMovXV", 0>;
-defm "" : LMULReadAdvance<"ReadVIMovXX", 0>;
-defm "" : LMULReadAdvance<"ReadVFMovVF", 0>;
-defm "" : LMULReadAdvance<"ReadVFMovFV", 0>;
-defm "" : LMULReadAdvance<"ReadVFMovFX", 0>;
+def : ReadAdvance<ReadVIMovVX, 0>;
+def : ReadAdvance<ReadVIMovXV, 0>;
+def : ReadAdvance<ReadVIMovXX, 0>;
+def : ReadAdvance<ReadVFMovVF, 0>;
+def : ReadAdvance<ReadVFMovFV, 0>;
+def : ReadAdvance<ReadVFMovFX, 0>;
defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
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