[PATCH] D149931: [RISCV] Rework how implied SP operands work in the disassembler. NFC
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue May 16 09:43:58 PDT 2023
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8f43c3f49ece: [RISCV] Rework how implied SP operands work in the disassembler. NFC (authored by craig.topper).
Changed prior to commit:
https://reviews.llvm.org/D149931?vs=519752&id=522669#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D149931/new/
https://reviews.llvm.org/D149931
Files:
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
Index: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
===================================================================
--- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -41,6 +41,9 @@
DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
ArrayRef<uint8_t> Bytes, uint64_t Address,
raw_ostream &CStream) const override;
+
+private:
+ void addSPOperands(MCInst &MI) const;
};
} // end anonymous namespace
@@ -267,30 +270,11 @@
return MCDisassembler::Success;
}
-// Add implied SP operand for instructions *SP compressed instructions. The SP
-// operand isn't explicitly encoded in the instruction.
-static void addImplySP(MCInst &Inst) {
- if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
- Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
- Inst.getOpcode() == RISCV::C_FLWSP ||
- Inst.getOpcode() == RISCV::C_FSWSP ||
- Inst.getOpcode() == RISCV::C_FLDSP ||
- Inst.getOpcode() == RISCV::C_FSDSP ||
- Inst.getOpcode() == RISCV::C_ADDI4SPN) {
- Inst.addOperand(MCOperand::createReg(RISCV::X2));
- }
- if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
- Inst.addOperand(MCOperand::createReg(RISCV::X2));
- Inst.addOperand(MCOperand::createReg(RISCV::X2));
- }
-}
-
template <unsigned N>
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
int64_t Address,
const MCDisassembler *Decoder) {
assert(isUInt<N>(Imm) && "Invalid immediate");
- addImplySP(Inst);
Inst.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -309,7 +293,6 @@
int64_t Address,
const MCDisassembler *Decoder) {
assert(isUInt<N>(Imm) && "Invalid immediate");
- addImplySP(Inst);
// Sign-extend the number in the bottom N bits of Imm
Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
return MCDisassembler::Success;
@@ -489,6 +472,15 @@
return MCDisassembler::Success;
}
+// Add implied SP operand for C.*SP compressed instructions. The SP operand
+// isn't explicitly encoded in the instruction.
+void RISCVDisassembler::addSPOperands(MCInst &MI) const {
+ const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
+ for (unsigned i = 0; i < MCID.getNumOperands(); i++)
+ if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
+ MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
+}
+
DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes,
uint64_t Address,
@@ -634,8 +626,10 @@
// Calling the auto-generated decoder function.
Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
this, STI);
- if (Result != MCDisassembler::Fail)
+ if (Result != MCDisassembler::Fail) {
+ addSPOperands(MI);
return Result;
+ }
}
if (STI.hasFeature(RISCV::FeatureStdExtZcmt)) {
LLVM_DEBUG(
@@ -657,5 +651,9 @@
LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
// Calling the auto-generated decoder function.
- return decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
+ Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
+ if (Result != MCDisassembler::Fail)
+ addSPOperands(MI);
+
+ return Result;
}
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