[PATCH] D149931: [RISCV] Rework how implied SP operands work in the disassembler. NFC

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM.



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Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:442
 
+// Add implied SP operand for instructions *SP compressed instructions. The SP
+// operand isn't explicitly encoded in the instruction.
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I know you just copied this from the previous function, but perhaps change to "Add implied SP operand for C.*SP compressed instructions. [...]"


Repository:
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  https://reviews.llvm.org/D149931/new/

https://reviews.llvm.org/D149931