[PATCH] D150107: [X86] Remove patterns for shift/rotate with immediate 1 and optimize during MC lowering

[Kan Shengchen via Phabricator via llvm-commits]

skan marked an inline comment as done.
skan added inline comments.


================
Comment at: llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp:151
+    return false;
+    FROM_TO(ROL8ri, ROR8r1, 7)
+    FROM_TO(ROR8ri, ROL8r1, 7)
----------------
craig.topper wrote:
> Are the flags the same? I don't think we ever use the flags from rotate, but since we're treating this like almost an assembler optimization we should probably know if we'll break any future flag usages.
> Are the flags the same? I don't think we ever use the flags from rotate, but since we're treating this like almost an assembler optimization we should probably know if we'll break any future flag usages.

Good point! The SPEC says


> For ROL and ROR instructions, if
> the masked count is 0, the flags are not affected. If the masked count is 1, then the OF flag is affected, otherwise
> (masked count is greater than 1) the OF flag is undefined.

So they have different impact on the flags. I will revert the related changes.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D150107/new/

https://reviews.llvm.org/D150107