[PATCH] D150381: [AMDGPU] Add optional tied-op for wwm-register's epilog spill restore

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1683
+    // ...
+    if (!IsStore && MBB.isReturnBlock() && isReturnValueCCReg(*MI, SubReg)) {
+      MIB.addReg(SubReg, RegState::Implicit);
----------------
arsenm wrote:
> Should replace this with a liveness query instead 
Using `LiveRegs` here won't help. The CSRs (including wwm-regs) are marked LiveOut by `initLiveRegs()` for an epilog block. In that sense, the liveness query will always hold true and we add the tied-op unconditionally for all spill reloads.
These registers are, in fact, liveout only after the insertion of the spill-restore. But we are in the process of inserting one, and we need to look one level backward to get their actual liveness. `LiveRegs` in its present form won't be helpful for that.

The intention of this patch is to tie the return value register to its own spill restore (if have one) to avoid an incorrect optimization currently performed on it due to the presence of the wwm-restore inserted afterward. 
Instead of walking through the operands of RETURN instruction, I would prefer if we have a utility function that returns a regmask or the list of return value registers allocated for this function. But not sure such a thing exists.


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  https://reviews.llvm.org/D150381/new/

https://reviews.llvm.org/D150381