[PATCH] D150381: [AMDGPU] Add optional tied-op for wwm-register's epilog spill restore

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

I noticed in the context we still have some forward scavenging. Those should have been replaced when we switched to using PEI in reverse.



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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1298
+  for (MachineOperand &MO : MI.operands()) {
+    if (MO.isReg() && MO.getReg() == Reg)
+      return true;
----------------
Exact register equality is almost always wrong 


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1683
+    // ...
+    if (!IsStore && MBB.isReturnBlock() && isReturnValueCCReg(*MI, SubReg)) {
+      MIB.addReg(SubReg, RegState::Implicit);
----------------
Should replace this with a liveness query instead 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D150381/new/

https://reviews.llvm.org/D150381