[llvm] ad8765a - Revert "[RISCV][llvm-mca] Add mca tests for riscv lmul instruments"
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Fri May 12 09:23:29 PDT 2023
Author: Michael Maitland
Date: 2023-05-12T09:23:19-07:00
New Revision: ad8765a0c8f44311b75d9965472be9aca49a37ab
URL: https://github.com/llvm/llvm-project/commit/ad8765a0c8f44311b75d9965472be9aca49a37ab
DIFF: https://github.com/llvm/llvm-project/commit/ad8765a0c8f44311b75d9965472be9aca49a37ab.diff
LOG: Revert "[RISCV][llvm-mca] Add mca tests for riscv lmul instruments"
This commit passed buildable tests in phabricator, but fails once
committed.
This reverts commit 1dedc96d04c82e29fff18ee3b875505a158ff93c.
Added:
Modified:
Removed:
llvm/test/tools/llvm-mca/RISCV/different-instruments.s
llvm/test/tools/llvm-mca/RISCV/disable-im.s
llvm/test/tools/llvm-mca/RISCV/instrument-at-start.s
llvm/test/tools/llvm-mca/RISCV/instrument-in-middle.s
llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s
llvm/test/tools/llvm-mca/RISCV/instrument-straddles-region.s
llvm/test/tools/llvm-mca/RISCV/multiple-same-instruments.s
llvm/test/tools/llvm-mca/RISCV/riscv-instrument-no-data-is-err.s
llvm/test/tools/llvm-mca/RISCV/unknown-instrument-is-err.s
llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s
################################################################################
diff --git a/llvm/test/tools/llvm-mca/RISCV/
diff erent-instruments.s b/llvm/test/tools/llvm-mca/RISCV/
diff erent-instruments.s
deleted file mode 100644
index ced206a923e1b..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/
diff erent-instruments.s
+++ /dev/null
@@ -1,76 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-LMUL M1
-vadd.vv v12, v12, v12
-vsetvli zero, a0, e8, m8, tu, mu
-# LLVM-MCA-RISCV-LMUL M8
-vadd.vv v12, v12, v12
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 4
-# CHECK-NEXT: Total Cycles: 12
-# CHECK-NEXT: Total uOps: 4
-
-# CHECK: Dispatch Width: 2
-# CHECK-NEXT: uOps Per Cycle: 0.33
-# CHECK-NEXT: IPC: 0.33
-# CHECK-NEXT: Block RThroughput: 18.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
-# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFive7FDiv
-# CHECK-NEXT: [1] - SiFive7IDiv
-# CHECK-NEXT: [2] - SiFive7PipeA
-# CHECK-NEXT: [3] - SiFive7PipeB
-# CHECK-NEXT: [4] - SiFive7PipeV
-# CHECK-NEXT: [5] - SiFive7VA
-# CHECK-NEXT: [6] - SiFive7VL
-# CHECK-NEXT: [7] - SiFive7VS
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - - 2.00 - 18.00 18.00 - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
-# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
-# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
-
-# CHECK: Timeline view:
-# CHECK-NEXT: 01
-# CHECK-NEXT: Index 0123456789
-
-# CHECK: [0,0] DeeE . .. vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: [0,1] . DeeeE .. vadd.vv v12, v12, v12
-# CHECK-NEXT: [0,2] . DeeE .. vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: [0,3] . . DeeeE vadd.vv v12, v12, v12
-
-# CHECK: Average Wait times (based on the timeline view):
-# CHECK-NEXT: [0]: Executions
-# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
-# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
-# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
-
-# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
-# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
-# CHECK-NEXT: 1 0.0 0.0 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/disable-im.s b/llvm/test/tools/llvm-mca/RISCV/disable-im.s
deleted file mode 100644
index fc969bf7c99aa..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/disable-im.s
+++ /dev/null
@@ -1,87 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 -disable-im < %s | FileCheck %s
-
-vsetvli zero, a0, e8, m2, tu, mu
-# LLVM-MCA-RISCV-LMUL M2
-vadd.vv v12, v12, v12
-vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-LMUL M1
-vadd.vv v12, v12, v12
-vsetvli zero, a0, e8, m8, tu, mu
-# LLVM-MCA-RISCV-LMUL M8
-vadd.vv v12, v12, v12
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 6
-# CHECK-NEXT: Total Cycles: 40
-# CHECK-NEXT: Total uOps: 6
-
-# CHECK: Dispatch Width: 2
-# CHECK-NEXT: uOps Per Cycle: 0.15
-# CHECK-NEXT: IPC: 0.15
-# CHECK-NEXT: Block RThroughput: 48.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m2, tu, mu
-# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
-# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
-# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFive7FDiv
-# CHECK-NEXT: [1] - SiFive7IDiv
-# CHECK-NEXT: [2] - SiFive7PipeA
-# CHECK-NEXT: [3] - SiFive7PipeB
-# CHECK-NEXT: [4] - SiFive7PipeV
-# CHECK-NEXT: [5] - SiFive7VA
-# CHECK-NEXT: [6] - SiFive7VL
-# CHECK-NEXT: [7] - SiFive7VS
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - - 3.00 - 48.00 48.00 - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
-# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m2, tu, mu
-# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
-# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
-# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
-
-# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789 0123456789
-# CHECK-NEXT: Index 0123456789 0123456789
-
-# CHECK: [0,0] DeeE . . . . . . . . vsetvli zero, a0, e8, m2, tu, mu
-# CHECK-NEXT: [0,1] . DeeeE . . . . . . . vadd.vv v12, v12, v12
-# CHECK-NEXT: [0,2] . DeeE . . . . . . . vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: [0,3] . . . . DeeeE . . . . vadd.vv v12, v12, v12
-# CHECK-NEXT: [0,4] . . . . DeeE . . . . vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: [0,5] . . . . . . . DeeeE vadd.vv v12, v12, v12
-
-# CHECK: Average Wait times (based on the timeline view):
-# CHECK-NEXT: [0]: Executions
-# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
-# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
-# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
-
-# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m2, tu, mu
-# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
-# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
-# CHECK-NEXT: 4. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: 5. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
-# CHECK-NEXT: 1 0.0 0.0 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/instrument-at-start.s b/llvm/test/tools/llvm-mca/RISCV/instrument-at-start.s
deleted file mode 100644
index fd33e2adacb8c..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/instrument-at-start.s
+++ /dev/null
@@ -1,64 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-LMUL M1
-vadd.vv v12, v12, v12
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 2
-# CHECK-NEXT: Total Cycles: 8
-# CHECK-NEXT: Total uOps: 2
-
-# CHECK: Dispatch Width: 2
-# CHECK-NEXT: uOps Per Cycle: 0.25
-# CHECK-NEXT: IPC: 0.25
-# CHECK-NEXT: Block RThroughput: 2.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFive7FDiv
-# CHECK-NEXT: [1] - SiFive7IDiv
-# CHECK-NEXT: [2] - SiFive7PipeA
-# CHECK-NEXT: [3] - SiFive7PipeB
-# CHECK-NEXT: [4] - SiFive7PipeV
-# CHECK-NEXT: [5] - SiFive7VA
-# CHECK-NEXT: [6] - SiFive7VL
-# CHECK-NEXT: [7] - SiFive7VS
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - - 1.00 - 2.00 2.00 - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
-# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
-
-# CHECK: Timeline view:
-# CHECK-NEXT: Index 01234567
-
-# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12
-
-# CHECK: Average Wait times (based on the timeline view):
-# CHECK-NEXT: [0]: Executions
-# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
-# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
-# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
-
-# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
-# CHECK-NEXT: 1 0.0 0.0 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/instrument-in-middle.s b/llvm/test/tools/llvm-mca/RISCV/instrument-in-middle.s
deleted file mode 100644
index 90fe5c655fbe9..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/instrument-in-middle.s
+++ /dev/null
@@ -1,70 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
-
-vadd.vv v12, v12, v12
-vsetvli zero, a0, e8, m8, tu, mu
-# LLVM-MCA-RISCV-LMUL MF8
-vadd.vv v12, v12, v12
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 3
-# CHECK-NEXT: Total Cycles: 21
-# CHECK-NEXT: Total uOps: 3
-
-# CHECK: Dispatch Width: 2
-# CHECK-NEXT: uOps Per Cycle: 0.14
-# CHECK-NEXT: IPC: 0.14
-# CHECK-NEXT: Block RThroughput: 17.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
-# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFive7FDiv
-# CHECK-NEXT: [1] - SiFive7IDiv
-# CHECK-NEXT: [2] - SiFive7PipeA
-# CHECK-NEXT: [3] - SiFive7PipeB
-# CHECK-NEXT: [4] - SiFive7PipeV
-# CHECK-NEXT: [5] - SiFive7VA
-# CHECK-NEXT: [6] - SiFive7VL
-# CHECK-NEXT: [7] - SiFive7VS
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - - 1.00 - 17.00 17.00 - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
-# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
-# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vv v12, v12, v12
-
-# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 0
-
-# CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12
-# CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12
-
-# CHECK: Average Wait times (based on the timeline view):
-# CHECK-NEXT: [0]: Executions
-# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
-# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
-# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
-
-# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
-# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
-# CHECK-NEXT: 1 0.0 0.0 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s b/llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s
deleted file mode 100644
index f33ae272f310f..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s
+++ /dev/null
@@ -1,68 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
-
-# LLVM-MCA-BEGIN foo
-vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-LMUL M1
-vadd.vv v12, v12, v12
-# LLVM-MCA-END foo
-
-# CHECK: [0] Code Region - foo
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 2
-# CHECK-NEXT: Total Cycles: 8
-# CHECK-NEXT: Total uOps: 2
-
-# CHECK: Dispatch Width: 2
-# CHECK-NEXT: uOps Per Cycle: 0.25
-# CHECK-NEXT: IPC: 0.25
-# CHECK-NEXT: Block RThroughput: 2.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFive7FDiv
-# CHECK-NEXT: [1] - SiFive7IDiv
-# CHECK-NEXT: [2] - SiFive7PipeA
-# CHECK-NEXT: [3] - SiFive7PipeB
-# CHECK-NEXT: [4] - SiFive7PipeV
-# CHECK-NEXT: [5] - SiFive7VA
-# CHECK-NEXT: [6] - SiFive7VL
-# CHECK-NEXT: [7] - SiFive7VS
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - - 1.00 - 2.00 2.00 - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
-# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
-
-# CHECK: Timeline view:
-# CHECK-NEXT: Index 01234567
-
-# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12
-
-# CHECK: Average Wait times (based on the timeline view):
-# CHECK-NEXT: [0]: Executions
-# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
-# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
-# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
-
-# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
-# CHECK-NEXT: 1 0.0 0.0 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/instrument-straddles-region.s b/llvm/test/tools/llvm-mca/RISCV/instrument-straddles-region.s
deleted file mode 100644
index c2187a3838f6c..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/instrument-straddles-region.s
+++ /dev/null
@@ -1,69 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
-
-# LLVM-MCA-BEGIN foo
-vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-LMUL M1
-vadd.vv v12, v12, v12
-# LLVM-MCA-END foo
-vadd.vv v12, v12, v12
-
-# CHECK: [0] Code Region - foo
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 2
-# CHECK-NEXT: Total Cycles: 8
-# CHECK-NEXT: Total uOps: 2
-
-# CHECK: Dispatch Width: 2
-# CHECK-NEXT: uOps Per Cycle: 0.25
-# CHECK-NEXT: IPC: 0.25
-# CHECK-NEXT: Block RThroughput: 2.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFive7FDiv
-# CHECK-NEXT: [1] - SiFive7IDiv
-# CHECK-NEXT: [2] - SiFive7PipeA
-# CHECK-NEXT: [3] - SiFive7PipeB
-# CHECK-NEXT: [4] - SiFive7PipeV
-# CHECK-NEXT: [5] - SiFive7VA
-# CHECK-NEXT: [6] - SiFive7VL
-# CHECK-NEXT: [7] - SiFive7VS
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - - 1.00 - 2.00 2.00 - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
-# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
-
-# CHECK: Timeline view:
-# CHECK-NEXT: Index 01234567
-
-# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12
-
-# CHECK: Average Wait times (based on the timeline view):
-# CHECK-NEXT: [0]: Executions
-# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
-# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
-# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
-
-# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
-# CHECK-NEXT: 1 0.0 0.0 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/multiple-same-instruments.s b/llvm/test/tools/llvm-mca/RISCV/multiple-same-instruments.s
deleted file mode 100644
index 585908e760961..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/multiple-same-instruments.s
+++ /dev/null
@@ -1,97 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-LMUL M1
-vadd.vv v12, v12, v12
-vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-LMUL M1
-vadd.vv v12, v12, v12
-vsub.vv v12, v12, v12
-vsetvli zero, a0, e8, m2, tu, mu
-# LLVM-MCA-RISCV-LMUL M4
-vadd.vv v12, v12, v12
-vsub.vv v12, v12, v12
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 8
-# CHECK-NEXT: Total Cycles: 28
-# CHECK-NEXT: Total uOps: 8
-
-# CHECK: Dispatch Width: 2
-# CHECK-NEXT: uOps Per Cycle: 0.29
-# CHECK-NEXT: IPC: 0.29
-# CHECK-NEXT: Block RThroughput: 22.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
-# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
-# CHECK-NEXT: 1 4 16.00 vsub.vv v12, v12, v12
-# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m2, tu, mu
-# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
-# CHECK-NEXT: 1 4 16.00 vsub.vv v12, v12, v12
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFive7FDiv
-# CHECK-NEXT: [1] - SiFive7IDiv
-# CHECK-NEXT: [2] - SiFive7PipeA
-# CHECK-NEXT: [3] - SiFive7PipeB
-# CHECK-NEXT: [4] - SiFive7PipeV
-# CHECK-NEXT: [5] - SiFive7VA
-# CHECK-NEXT: [6] - SiFive7VL
-# CHECK-NEXT: [7] - SiFive7VS
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - - 3.00 - 22.00 22.00 - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
-# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
-# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
-# CHECK-NEXT: - - - - 2.00 2.00 - - vsub.vv v12, v12, v12
-# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m2, tu, mu
-# CHECK-NEXT: - - - - 8.00 8.00 - - vadd.vv v12, v12, v12
-# CHECK-NEXT: - - - - 8.00 8.00 - - vsub.vv v12, v12, v12
-
-# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
-# CHECK-NEXT: Index 0123456789 01234567
-
-# CHECK: [0,0] DeeE . . . . . . vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: [0,1] . DeeeE . . . . . vadd.vv v12, v12, v12
-# CHECK-NEXT: [0,2] . DeeE . . . . . vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: [0,3] . . DeeeE . . . . vadd.vv v12, v12, v12
-# CHECK-NEXT: [0,4] . . .DeeeE . . . vsub.vv v12, v12, v12
-# CHECK-NEXT: [0,5] . . . DeeE . . . vsetvli zero, a0, e8, m2, tu, mu
-# CHECK-NEXT: [0,6] . . . DeeeE. . . vadd.vv v12, v12, v12
-# CHECK-NEXT: [0,7] . . . . . DeeeE vsub.vv v12, v12, v12
-
-# CHECK: Average Wait times (based on the timeline view):
-# CHECK-NEXT: [0]: Executions
-# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
-# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
-# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
-
-# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
-# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
-# CHECK-NEXT: 4. 1 0.0 0.0 0.0 vsub.vv v12, v12, v12
-# CHECK-NEXT: 5. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m2, tu, mu
-# CHECK-NEXT: 6. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
-# CHECK-NEXT: 7. 1 0.0 0.0 0.0 vsub.vv v12, v12, v12
-# CHECK-NEXT: 1 0.0 0.0 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/riscv-instrument-no-data-is-err.s b/llvm/test/tools/llvm-mca/RISCV/riscv-instrument-no-data-is-err.s
deleted file mode 100644
index ac5b0f8ead0a2..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/riscv-instrument-no-data-is-err.s
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
-
-vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-LMUL
-vadd.vv v12, v12, v12
-
-# CHECK: error: Failed to create RISCV-LMUL instrument with no data
-# CHECK: # LLVM-MCA-RISCV-LMUL
-# CHECK: ^
-# CHECK: error: There was an error parsing comments.
diff --git a/llvm/test/tools/llvm-mca/RISCV/unknown-instrument-is-err.s b/llvm/test/tools/llvm-mca/RISCV/unknown-instrument-is-err.s
deleted file mode 100644
index 90675462d4740..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/unknown-instrument-is-err.s
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s 2>&1 | FileCheck %s
-
-# LLVM-MCA-UNKNOWN M1
-vsetvli zero, a0, e8, m1, tu, mu
-vadd.vv v12, v12, v12
-
-# CHECK: error: Unknown instrumentation type in LLVM-MCA comment: UNKNOWN
-# CHECK: # LLVM-MCA-UNKNOWN M1
-# CHECK: ^
-# CHECK: error: There was an error parsing comments.
diff --git a/llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s b/llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s
deleted file mode 100644
index ef080182f7001..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
-
-vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-V MF9
-vadd.vv v12, v12, v12
-
-# CHECK: error: Unknown instrumentation type in LLVM-MCA comment: RISCV-V
-# CHECK: # LLVM-MCA-RISCV-V MF9
-# CHECK: ^
-# CHECK: error: There was an error parsing comments.
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