[PATCH] D150246: AMDGPU: Fix issue in shl(or) combine

[Ruiling, Song via Phabricator via llvm-commits]

ruiling added a comment.

In D150246#4337140 <https://reviews.llvm.org/D150246#4337140>, @arsenm wrote:

> Is there a negative test for the common bits case?

I have added one: shl_or_ptr_not_combine_2use_lds



================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:9577
   // multiple uses of the add, so defer to the standard combine.
-  if ((N0.getOpcode() != ISD::ADD && N0.getOpcode() != ISD::OR) ||
+  if ((N0.getOpcode() != ISD::ADD && N0->getOpcode() != ISD::OR) ||
       N0->hasOneUse())
----------------
arsenm wrote:
> Don’t know why this has to change 
I don't know what happened:( will fix it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150246/new/

https://reviews.llvm.org/D150246