[PATCH] D150246: AMDGPU: Fix issue in shl(or) combine

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added a comment.
This revision is now accepted and ready to land.

Is there a negative test for the common bits case?



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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:9577
   // multiple uses of the add, so defer to the standard combine.
-  if ((N0.getOpcode() != ISD::ADD && N0.getOpcode() != ISD::OR) ||
+  if ((N0.getOpcode() != ISD::ADD && N0->getOpcode() != ISD::OR) ||
       N0->hasOneUse())
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Don’t know why this has to change 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150246/new/

https://reviews.llvm.org/D150246