[PATCH] D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen

[luxufan via Phabricator via llvm-commits]

StephenFan added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:279
+    const auto &STI = MF->getSubtarget<RISCVSubtarget>();
+    assert(!STI.enableUnalignedScalarMem());
+
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I don't think we need to assert unaligned scalar memory feature is not enabled. Since `RISCVDAGToDAGISel::SelectAddrRegImm` has ensured that the global value's alignment must be greater than the result of `getOffset()` even when the unaligned scalar memory feature is enabled.


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https://reviews.llvm.org/D149743