[PATCH] D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:281
+
+    assert(MBBI->getOperand(2).getOffset() == 0);
+    MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
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I dont' think the offset is guaranteed to be 0. RISCVDAGToDAGISel::SelectAddrRegImm can update the offset when the address is formed. I think you can assume `getOffset() % 8 == 0` which is enough for the +4 to not overflow.


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Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:298
+          .addImm(4);
+      BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
+          .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
----------------
It's possible that operand 1 and Hi are the same register. If they are, the +4  to operand 1 will cause Hi to be the wrong value when you store it.


Repository:
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  https://reviews.llvm.org/D149743/new/

https://reviews.llvm.org/D149743