[PATCH] D149732: [RISCV] Fix extract_vector_elt on i1 at idx 0 being inverted

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I think SETEQ was correct before. We're checking the result of vfirst which can return a value between [-1, VL). We want to know specifically if bit 0 is set. There are 3 cases to consider. If bit 0 is set the result of the first will be 0. If bit 0 is not set but some other bit is the result of the vfirst will be >0. The third case is that bit 0 isn't set and no other bits are set. In that case the vfirst will return -1.

The first case is the only case we should return 1. So we should be checking that the result of the vfirst is equal to 0, the original code before this patch.


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  https://reviews.llvm.org/D149732/new/

https://reviews.llvm.org/D149732