[PATCH] D150177: [RISCV] Enable signed truncation check transforms for i8

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/signed-truncation-check.ll:468
   %tmp0 = add i64 %x, -128 ; ~0U << (8-1)
   %tmp1 = icmp uge i64 %tmp0, -256 ; ~0U << 8
   ret i1 %tmp1
----------------
This IR is non-canonical. We shouldn't get a uge with constant from InstCombine. I'll add more tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150177/new/

https://reviews.llvm.org/D150177