[PATCH] D150177: [RISCV] Enable signed truncation check transforms for i8

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll:401
+; RV32I-NEXT:    sltu a0, a2, a0
+; RV32I-NEXT:    add a0, a1, a0
+; RV32I-NEXT:    addi a0, a0, -1
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These two instructions are an odd variant of the add-carry from below.  This looks like something got turned into a select whereas the add-with-carry + compare-two-halves should have worked here.


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Comment at: llvm/test/CodeGen/RISCV/signed-truncation-check.ll:651
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a2, a0, 128
+; RV32I-NEXT:    sltu a0, a2, a0
----------------
This code sequence actually looks pretty good.  It's the straight forward "add-carry-and compare" scheme. 

Have you looked at why the inverted form of this check doesn't get canonicalized towards this form?  If it did, we might get better codegen overall.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150177/new/

https://reviews.llvm.org/D150177