[PATCH] D150135: [RISCV] Improve RV64 codegen for i32 ISD::SADDO when RHS is constant.

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9041
+
+    // If the RHS is a constant, we can simplify ConditionRHS below. Otherwise
+    // use the default legalization.
----------------
The uaddo case below uses a comparison of two add flavors.  Does the same notion work here for the non-constant case?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9046
+
+    SDValue LHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, N->getOperand(0));
+    SDValue RHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, N->getOperand(1));
----------------
The uaddo/usubo case just below uses any_extend here, can we get away with the same?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D150135/new/

https://reviews.llvm.org/D150135