[PATCH] D150135: [RISCV] Improve RV64 codegen for i32 ISD::SADDO when RHS is constant.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 8 12:06:25 PDT 2023
craig.topper created this revision.
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This uses the same sequence we get from LegalizeDAG for i32 on RV32, but modified
to use W instructions.
When the RHS is constant one of the setccs simplifies to a constant and the xor will either
be an xori with 1 or get removed. Not constants cases were a less obvious improvement
especially when we branch on overflow.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D150135
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/xaluo.ll
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