[PATCH] D141485: [X86] Add schedule module for SapphireRapids
Noah Goldstein via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 8 10:40:24 PDT 2023
goldstein.w.n added a comment.
In D141485#4043332 <https://reviews.llvm.org/D141485#4043332>, @HaohaiWen wrote:
> Instruction's scheduling info in this model comes from many sources.
> Priority of source is (dsc order)
>
> 1. 4th Generation Intel® Xeon® Scalable Processor Family (based on Sapphire Rapids Architecture) Instruction Throughput and Latency in https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
> 2. Alderlake-P data from uops.info
> 3. Current SkylakeServerModel.
Why skylake server as opposed to ICX server?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D141485/new/
https://reviews.llvm.org/D141485
More information about the llvm-commits
mailing list