[PATCH] D141485: [X86] Add schedule module for SapphireRapids

[Haohai, Wen via Phabricator via llvm-commits]

HaohaiWen marked 2 inline comments as done.
HaohaiWen added inline comments.


================
Comment at: llvm/lib/Target/X86/X86SchedSapphireRapids.td:68
+def SPRPort00_01_05_06_10 : ProcResGroup<[SPRPort00, SPRPort01, SPRPort05,
+                                          SPRPort06, SPRPort10]> {
+  let BufferSize = 112;
----------------
LuoYuanke wrote:
> Port10 or port11?
Port 10 is ALU+LEA which is same group as 0, 1, 5, 6
Port 11 is AGU+Load which is same group as 2, 3, 7, 8


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  https://reviews.llvm.org/D141485/new/

https://reviews.llvm.org/D141485