[PATCH] D150021: [RISCV] Make zve32f imply F and zve64d imply D.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG728b8a139804: [RISCV] Make zve32f imply F and zve64d imply D. (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D150021?vs=520038&id=520150#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150021/new/

https://reviews.llvm.org/D150021

Files:
  clang/test/Driver/riscv-arch.c
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td

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