[PATCH] D149833: [X86][AsmParser] Omit predicate In64BitMode for instructions w/ GP64 operand in X86InstrArithmetic.td, NFCI

[Kan Shengchen via Phabricator via llvm-commits]

skan abandoned this revision.
skan added inline comments.


================
Comment at: llvm/lib/Target/X86/X86InstrArithmetic.td:602
   def INC32m : INCDECM<MRM0m, "inc", Xi32, 1>;
-} // Predicates
-let Predicates = [UseIncDec, In64BitMode] in {
   def INC64m : INCDECM<MRM0m, "inc", Xi64, 1>;
+} // CodeSize = 2, SchedRW, Predicates
----------------
craig.topper wrote:
> skan wrote:
> > craig.topper wrote:
> > > This instruction doesn't have a GPR operand. It's just `incq (%rax)` If the pointer doesn't have any register or uses 32 bit registers what prevents it from parsing?
> > > This instruction doesn't have a GPR operand. It's just `incq (%rax)` If the pointer doesn't have any register or uses 32 bit registers what prevents it from parsing?
> > 
> > @craig.topper We can check if W bit is set.
> Why create a new way to do this when we already have predicates?
I intended to simplify the code in TD. But I agreed that it would make the code in AsmParser look worse. I will close this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149833/new/

https://reviews.llvm.org/D149833