[PATCH] D149977: [RISCV] Implement shouldTransformSignedTruncationCheck.

[Yingwei Zheng via Phabricator via llvm-commits]

dtcxzyw added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:12172
+  // With Zbb we can use sext.h. sext.b does not seem to be profitable.
+  return Subtarget.hasStdExtZbb() && KeptBits == 16;
+}
----------------
We can enable this for i8 on rv32 when XVT is i64 and Zbb is enabled.
Before:
```
; RV32I-LABEL: add_ultcmp_i64_i8:
; RV32I:       # %bb.0:
; RV32I-NEXT:    addi a2, a0, -128
; RV32I-NEXT:    sltu a0, a2, a0
; RV32I-NEXT:    add a0, a1, a0
; RV32I-NEXT:    addi a0, a0, -1
; RV32I-NEXT:    li a1, -1
; RV32I-NEXT:    beq a0, a1, .LBB11_2
; RV32I-NEXT:  # %bb.1:
; RV32I-NEXT:    sltiu a0, a0, -1
; RV32I-NEXT:    ret
; RV32I-NEXT:  .LBB11_2:
; RV32I-NEXT:    sltiu a0, a2, -256
; RV32I-NEXT:    ret
```
After:
```
; RV32ZBB-LABEL: add_ultcmp_i64_i8:
; RV32ZBB:       # %bb.0:
; RV32ZBB-NEXT:    sext.b a2, a0
; RV32ZBB-NEXT:    xor a0, a2, a0
; RV32ZBB-NEXT:    srai a2, a2, 31
; RV32ZBB-NEXT:    xor a1, a2, a1
; RV32ZBB-NEXT:    or a0, a0, a1
; RV32ZBB-NEXT:    snez a0, a0
; RV32ZBB-NEXT:    ret
```



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149977/new/

https://reviews.llvm.org/D149977