[PATCH] D149486: [RISCV] Strengthen atomic ordering for sequentially consistent stores

[Hans Boehm via Phabricator via llvm-commits]

hboehm added a comment.

I replied to jrtc27's comment in the psABI discussion at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/378 .

Re: Paul's concern about LR.aq; SC.rl not acting as a fence: That feature is shared by C and C++ atomic operations, so it should be perfectly fine for the translation. If I write in C++:

`r1 = x.load(memory_order_relaxed);`
`y.fetch_add(1, memory_order_seq_cst);`
`r2 = z.load(memory_order_relaxed);`

the loads from x and z can be reordered. `fetch_add()` is not a fence either.

This is desirable for two reasons:
(1) It makes atomics implementable with conventional locks (`lock(); unlock()` is also not a fence), and
(2) It allows cheaper seq_cst implementations that still preserve the property that if you only use seq_cst operations and locks you get sequentiial consistency.


Repository:
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https://reviews.llvm.org/D149486