[PATCH] D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:284
+  } else {
+    assert(MBBI->getOperand(2).getImm() < 0x7fc);
+    BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
----------------
I am trying another solution, help to see, will it have any potential problems?  @jrtc27, thanks.
```
 else {
     Register TmpReg = MBBI->getOperand(1).getReg();
    BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), TmpReg)
         .add(MBBI->getOperand(1))
         .addImm(4);
    BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
        .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
        .add(MBBI->getOperand(1))
        .add(MBBI->getOperand(2));
  }
```


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D149743