[PATCH] D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen
Jessica Clarke via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 4 23:40:30 PDT 2023
jrtc27 added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoD.td:517
+let isCall = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in
+def PseudoRV32ZdinxLD : Pseudo<(outs GPRPF64:$dst), (ins GPR:$rs1, simm12:$imm12), []>;
+defm : LdPat<load, PseudoRV32ZdinxLD, f64>;
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liaolucy wrote:
>
> We might add def simm12_sub4, the range is [-2048,2023]. Then replace simm12 with simm12_sub4.
That doesn’t help you, globals etc are still broken.
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D149743/new/
https://reviews.llvm.org/D149743
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