[PATCH] D148347: [AArch64] Handle vector with two different values

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:12545
+    //    t30: v8i8 = AArch64ISD::DUP t26
+    //  t31: v8i8 = vector_shuffle<0,0,0,0,8,8,8,8> t28, t30
+    if (NumElts >= 8) {
----------------
dmgreen wrote:
> Would it help if this mask is `<0,1,2,3,12,13,14,15>` or `<0,1,2,3,8,9,10,11>`? I'm not sure it would help at the moment, but this case with i8's could use 's' lane inserts to avoid the tbl. It wouldn't help in general though.
Thanks for comment.
This code handles the vector with only two different values so the case with the mask <0,1,2,3,12,13,14,15> and <0,1,2,3,8,9,10,11> will not meet this code.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148347/new/

https://reviews.llvm.org/D148347