[PATCH] D148347: [AArch64] Handle vector with two different values

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri May 5 05:00:18 PDT 2023

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

I think the code looks OK. You may want to add some extra test cases that generate tbl though to show more cases.

Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:12545
+    //    t30: v8i8 = AArch64ISD::DUP t26
+    //  t31: v8i8 = vector_shuffle<0,0,0,0,8,8,8,8> t28, t30
+    if (NumElts >= 8) {
Would it help if this mask is `<0,1,2,3,12,13,14,15>` or `<0,1,2,3,8,9,10,11>`? I'm not sure it would help at the moment, but this case with i8's could use 's' lane inserts to avoid the tbl. It wouldn't help in general though.



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