[PATCH] D149724: [RISCV] Promote i1 shuffles to i8 shuffles.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3815
+    return DAG.getSetCC(DL, VT, Shuffled, DAG.getConstant(0, DL, WidenVT),
+                        ISD::SETNE);
+  }
----------------
luke wrote:
> Can widenVectorOpsToi8 be reused here? It uses truncates instead of setcc, I'm not sure if that changes the resulting code
Using SETCC avoids a vand.vi instruction from the truncate lowering that looked unnecessary to me. That probably applies to VECTOR_REVERSE, VECTOR_INTERLEAVE, and VECTOR_DEINTERLEAVE too.

The main issue preventing using widenVectorOpsToi8 is that we can't create a shuffle with getNode. We have to call getVectorShuffle because the Mask isn't part of the operand list.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149724/new/

https://reviews.llvm.org/D149724