[PATCH] D149724: [RISCV] Promote i1 shuffles to i8 shuffles.

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3815
+    return DAG.getSetCC(DL, VT, Shuffled, DAG.getConstant(0, DL, WidenVT),
+                        ISD::SETNE);
+  }
----------------
Can widenVectorOpsToi8 be reused here? It uses truncates instead of setcc, I'm not sure if that changes the resulting code


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149724/new/

https://reviews.llvm.org/D149724