[llvm] 181d039 - [RISCV] Add missing constraints for vwsll

[via llvm-commits]

Author: 4vtomat
Date: 2023-05-01T22:09:29-07:00
New Revision: 181d0399e2243c793618cb2a322d8043dece7089

URL: https://github.com/llvm/llvm-project/commit/181d0399e2243c793618cb2a322d8043dece7089
DIFF: https://github.com/llvm/llvm-project/commit/181d0399e2243c793618cb2a322d8043dece7089.diff

LOG: [RISCV] Add missing constraints for vwsll

Add missing early clobber and widen constraints for vector crypto instruction: vwsll

Differential Revision: https://reviews.llvm.org/D149127

Added: 
    llvm/test/MC/RISCV/rvv/zvbb-invalid.s

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 1e27e4306b840..ea7240af691cd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -138,6 +138,7 @@ let Predicates = [HasStdExtZvbb] in {
   def  VREV8_V  : VALUVs2<0b010010, 0b01001, OPMVV, "vrev8.v">;
   defm VROL_V   : VALU_IV_V_X<"vrol", 0b010101>;
   defm VROR_V   : VROR_IV_V_X_I<"vror", 0b010100>;
+  let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in
   defm VWSLL_V  : VALU_IV_V_X_I<"vwsll", 0b110101, uimm5>;
 } // Predicates = [HasStdExtZvbb]
 

diff  --git a/llvm/test/MC/RISCV/rvv/zvbb-invalid.s b/llvm/test/MC/RISCV/rvv/zvbb-invalid.s
new file mode 100644
index 0000000000000..46bde3a8ce702
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvbb-invalid.s
@@ -0,0 +1,14 @@
+# RUN: not llvm-mc -triple=riscv64 --mattr=+zve64x --mattr=+experimental-zvbb %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+vwsll.vv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsll.vv v2, v2, v4
+
+vwsll.vx v2, v2, x10
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsll.vx v2, v2, x10
+
+vwsll.vi v2, v2, 1
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsll.vi v2, v2, 1