[PATCH] D149552: [JITLink][RISCV] Fix logic for R_RISCV_ALIGN

[Jonas Hahnfeld via Phabricator via llvm-commits]

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The relocation's addend encodes the number of bytes with NOP
instructions, which is less than the required alignment. For
example, with compressed instructions, an alignment to 4 bytes
requires only one compressed NOP instruction of two bytes that
the linker can either leave in or remove. This actually means
that `R_RISCV_ALIGN` can never be ignored.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149552

Files:
  llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp


Index: llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
===================================================================
--- llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
+++ llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
@@ -550,16 +550,13 @@
 
     int64_t Addend = Rel.r_addend;
     if (Type == llvm::ELF::R_RISCV_ALIGN) {
-      uint64_t Alignment = PowerOf2Ceil(Addend);
+      uint64_t Alignment = NextPowerOf2(Addend);
       // FIXME: Implement support for ensuring alignment together with linker
-      // relaxation; 2 bytes are guaranteed by the length of compressed
-      // instructions, so this does not need any action from our side.
-      if (Alignment > 2)
-        return make_error<JITLinkError>(
-            formatv("Unsupported relocation R_RISCV_ALIGN with alignment {0} "
-                    "larger than 2 (addend: {1})",
-                    Alignment, Addend));
-      return Error::success();
+      // relaxation
+      return make_error<JITLinkError>(
+          formatv("Unsupported relocation R_RISCV_ALIGN with alignment {0} "
+                  "(offset: {1}, addend: {2})",
+                  Alignment, Rel.r_offset, Addend));
     }
 
     Expected<riscv::EdgeKind_riscv> Kind = getRelocationKind(Type);


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