[PATCH] D149375: [RISCV] Introduce unaligned-vector-mem feature

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D149375#4303396 <https://reviews.llvm.org/D149375#4303396>, @craig.topper wrote:

>> While making this change, I realized that we actually *do* support unaligned vector loads and stores of all types via conversion to i8 element type. For contiguous loads and stores, we actually already implement this in the backend - though we don't tell the optimizer that. For indexed, lowering to i8 requires complicated addressing. For indexed and segmented, we'd have to use indexed. All around, doesn't seem worthwhile pursuing, but makes for an interesting observation.
>
> I don't think we support unaligned using i8 for contiguous masked load/store or VP load/store.

You're correct about masking, and I didn't look at VP.  Masking could be handled, but isn't today.  For the moment, I just updated the comment in the commit and source.



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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll:410
 
 ; Shouldn't be combined because the resulting load would not be aligned
 define void @strided_unaligned(ptr %x, ptr %z, i64 %s) {
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craig.topper wrote:
> Might want to tweak this comment to mention unaligned-vector-mem
Deleted the comment.  Swear I did that before posting the patch, but seems not.


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https://reviews.llvm.org/D149375