[PATCH] D149369: [RISCV] Consolidate legality checking for strided load/store [nfc]

[Philip Reames via Phabricator via llvm-commits]

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Note that the strided load from concat_vector combine was using the wrong legality test.  It happened to work out as the alignment requirement is based on the scalar type either way, but unless I'm missing something allowsMisalignedAccess is expecting a contiguous memory access.

Posting for review mostly to see if anyone had a better suggestion than getting the LLVM type from the VT.  That's a bit ugly, but I didn't see a cleaner way as the element type check is in terms of Type, not MVT.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149369

Files:
  llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h

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