[PATCH] D149358: [AMDGPU] Track liveins for max-ilp-sched-strategy

[Jeffrey Byrnes via Phabricator via llvm-commits]

jrbyrnes created this revision.
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Even if optimizing for ILP, it is still useful to track RP to avoid spilling. Given that, we need to maintin consistent liveness state with the RP tracker. This patch makes RP tracking consistent by updating for liveins.

Otherwise, we should completely eliminate RP tracking for this scheduler (checkScheduling, initCandidate).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149358

Files:
  llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
  llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir


Index: llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir
@@ -0,0 +1,34 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-enable-max-ilp-scheduling-strategy -verify-machineinstrs  -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
+
+---
+name:            max-ilp-liveness-tracking
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: max-ilp-liveness-tracking
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   %src0:vgpr_32 = V_MOV_B32_e64 0, implicit $exec
+  ; CHECK-NEXT:   %src1:vgpr_32 = V_MOV_B32_e64 1, implicit $exec
+  ; CHECK-NEXT:   %live0:vgpr_32 = V_ADD_U32_e32 %src0, %src1, implicit $exec
+  ; CHECK-NEXT:   %live1:vgpr_32 = V_ADD_U32_e32 %live0, %src1, implicit $exec
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   %out0:vgpr_32 = V_ADD_U32_e32 %live0, %live1, implicit $exec
+  ; CHECK-NEXT:   dead %out1:vgpr_32 = V_ADD_U32_e32 %out0, %live1, implicit $exec
+  ; CHECK-NEXT:   S_ENDPGM 0
+  bb.0:
+    successors: %bb.1
+    %src0:vgpr_32 = V_MOV_B32_e64 0, implicit $exec
+    %src1:vgpr_32 = V_MOV_B32_e64 1, implicit $exec
+    %live0:vgpr_32 = V_ADD_U32_e32 %src0:vgpr_32, %src1:vgpr_32, implicit $exec
+    %live1:vgpr_32 = V_ADD_U32_e32 %live0:vgpr_32, %src1:vgpr_32, implicit $exec
+
+  bb.1:
+    %out0:vgpr_32 = V_ADD_U32_e32 %live0:vgpr_32, %live1:vgpr_32, implicit $exec
+    %out1:vgpr_32 = V_ADD_U32_e32 %out0:vgpr_32, %live1:vgpr_32, implicit $exec
+    S_ENDPGM 0
+
+...
+
Index: llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -872,7 +872,8 @@
   DAG.startBlock(CurrentMBB);
   // Get real RP for the region if it hasn't be calculated before. After the
   // initial schedule stage real RP will be collected after scheduling.
-  if (StageID == GCNSchedStageID::OccInitialSchedule)
+  if (StageID == GCNSchedStageID::OccInitialSchedule ||
+      StageID == GCNSchedStageID::ILPInitialSchedule)
     DAG.computeBlockPressure(RegionIdx, CurrentMBB);
 }
 


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