[PATCH] D149263: [RISCV] Use vslide1down idiom for generic build_vector

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll:84-87
+; RV64-NEXT:    vslide1down.vx v8, v8, a0
+; RV64-NEXT:    vslide1down.vx v8, v8, a0
+; RV64-NEXT:    vslide1down.vx v8, v8, a0
+; RV64-NEXT:    vslide1down.vx v8, v8, a0
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This is interesting. The legalised DAG must be something like `build_vector <a4, a3, a2, a1, a0, undef, undef, undef>`.
Is there a potential combine we could do here to convert `n` nested `(vslide1down.vx v, undef)` into `(vslidedown.vi v, n)`?


Repository:
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  https://reviews.llvm.org/D149263/new/

https://reviews.llvm.org/D149263