[PATCH] D149263: [RISCV] Use vslide1down idiom for generic build_vector

[Philip Reames via Phabricator via llvm-commits]

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We had previously been going through the stack.

A couple small notes:

- We have the vslide1down idiom in a few other places.  As a post patch, I plan to try to common the code a bit.
- VF=2 case is still going through the splat + insert path.  Picking the optimal sequence for this seems to be a bit fiddly (due to constant mat costs), so I restricted this to cases which would have previously hit the stack.
- I'm only handling integer vectors for the moment.  Mostly because I don't see the existing vfslide1down ISD notes being in place.  This will be an obvious followup.
- One of the test diffs does expose a missing combine - a build_vector with a prefix coming from a vector extract sequence.  The code after this is arguably worse (due to domain crossing vs stack store), but I think this is a narrow enough case to be non-blocking for now.  Let me know if you disagree.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149263

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

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