[PATCH] D149063: [RISCV] Custom lowering of llvm.is.fpclass

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Can you add double and half to this patch? Doesn't seem like it would require very much additional code.



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4170
+  case ISD::IS_FPCLASS: {
+    SDLoc DL(Op);
+    MVT VT = Op.getSimpleValueType();
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Please put this in a separate function. We need to stop putting so much code into this switch.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.h:270
+const unsigned FPMASK_Negative_Normal = 0x002;
+const unsigned FPMASK_Negative_Infinity = 0x001;
 } // namespace RISCV
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Can you reverse the order here so we start with the least significant bit first.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoF.td:33
+def SDT_RISCVFPCLASS
+    : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVT<1, f32>]>;
+
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Don't use f32 here, you're going to need to change it for double and half. Just use SDTCisFP<1>


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https://reviews.llvm.org/D149063