[PATCH] D148316: [AArch64] Add support for efficient bitcast in vector truncate store.

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

> @dmgreen If you are concerned about legal types, should I add a check to only perform this before legalization?

It would be the other way around, performing the transform after legalization so that we know all types have been legalized. But that runs into the same issues as doing it during lowering. It is worth making sure there are tests for illegal types with odd number vector lanes and non-power2 integer types.



================
Comment at: llvm/test/CodeGen/AArch64/vec-combine-compare-truncate-store.ll:227
+
+define void @store_2_elements_64_bit_vector(<2 x i32> %vec, ptr %out) {
+; CHECK-LABEL: lCPI8_0:
----------------
Some of these with low vector lanes are starting to look worse than the code before. The fmov/strb could be done on the fp side, but I don't think that would be enough to make then profitable. Is it worth limiting it to >= 4 vector lanes?


Repository:
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https://reviews.llvm.org/D148316