[llvm] 15d2821 - [ARM] Fix qsat for armv5te/armv6 + thumb-mode
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 23 09:20:34 PDT 2023
Author: David Green
Date: 2023-04-23T17:20:28+01:00
New Revision: 15d28212632d550d437b8812c53a0e1f38aa4591
URL: https://github.com/llvm/llvm-project/commit/15d28212632d550d437b8812c53a0e1f38aa4591
DIFF: https://github.com/llvm/llvm-project/commit/15d28212632d550d437b8812c53a0e1f38aa4591.diff
LOG: [ARM] Fix qsat for armv5te/armv6 + thumb-mode
This is a Thumb1 target, so will not have qsat instructions available. There
was a mismatch between hasBaseDSP and the instruction patterns when +dsp was
present, which is set by clang (but maybe shouldn't be). The target being
thumb1-only should override that, implying that it does not have any qadds.
Fixes #62273
Added:
Modified:
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/test/CodeGen/ARM/sadd_sat.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 355128786c5b9..49a4025cae38c 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -5048,7 +5048,7 @@ SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
static SDValue LowerADDSUBSAT(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *Subtarget) {
EVT VT = Op.getValueType();
- if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
+ if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP() || Subtarget->isThumb1Only())
return SDValue();
if (!VT.isSimple())
return SDValue();
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 7e4d7a9b841a7..d9cc38e9e8cb4 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -348,7 +348,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
bool useSjLjEH() const { return UseSjLjEH; }
bool hasBaseDSP() const {
if (isThumb())
- return hasDSP();
+ return hasThumb2() && hasDSP();
else
return hasV5TEOps();
}
diff --git a/llvm/test/CodeGen/ARM/sadd_sat.ll b/llvm/test/CodeGen/ARM/sadd_sat.ll
index fc9cd2d5ef5b5..1632c4e86c762 100644
--- a/llvm/test/CodeGen/ARM/sadd_sat.ll
+++ b/llvm/test/CodeGen/ARM/sadd_sat.ll
@@ -1,10 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefixes=CHECK-T1,CHECK-T16
; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
; RUN: llc < %s -mtriple=armv5t-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMNODPS
; RUN: llc < %s -mtriple=armv5te-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMBASEDSP
; RUN: llc < %s -mtriple=armv5te-none-eabi -mattr=+dsp | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMBASEDSP
+; RUN: llc < %s -mtriple=armv5te-none-eabi -mattr=+dsp,thumb-mode | FileCheck %s --check-prefixes=CHECK-T1,CHECK-T15TE
+; RUN: llc < %s -mtriple=armv6-none-eabi -mattr=+dsp,thumb-mode | FileCheck %s --check-prefixes=CHECK-T1,CHECK-T16
; RUN: llc < %s -mtriple=armv6-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMDSP
declare i4 @llvm.sadd.sat.i4(i4, i4)
@@ -60,33 +62,33 @@ define i32 @func(i32 %x, i32 %y) nounwind {
}
define i64 @func2(i64 %x, i64 %y) nounwind {
-; CHECK-T1-LABEL: func2:
-; CHECK-T1: @ %bb.0:
-; CHECK-T1-NEXT: .save {r4, lr}
-; CHECK-T1-NEXT: push {r4, lr}
-; CHECK-T1-NEXT: mov r4, r1
-; CHECK-T1-NEXT: eors r1, r3
-; CHECK-T1-NEXT: adds r2, r0, r2
-; CHECK-T1-NEXT: adcs r3, r4
-; CHECK-T1-NEXT: eors r4, r3
-; CHECK-T1-NEXT: bics r4, r1
-; CHECK-T1-NEXT: asrs r1, r3, #31
-; CHECK-T1-NEXT: cmp r4, #0
-; CHECK-T1-NEXT: mov r0, r1
-; CHECK-T1-NEXT: bmi .LBB1_2
-; CHECK-T1-NEXT: @ %bb.1:
-; CHECK-T1-NEXT: mov r0, r2
-; CHECK-T1-NEXT: .LBB1_2:
-; CHECK-T1-NEXT: cmp r4, #0
-; CHECK-T1-NEXT: bmi .LBB1_4
-; CHECK-T1-NEXT: @ %bb.3:
-; CHECK-T1-NEXT: mov r1, r3
-; CHECK-T1-NEXT: pop {r4, pc}
-; CHECK-T1-NEXT: .LBB1_4:
-; CHECK-T1-NEXT: movs r2, #1
-; CHECK-T1-NEXT: lsls r2, r2, #31
-; CHECK-T1-NEXT: eors r1, r2
-; CHECK-T1-NEXT: pop {r4, pc}
+; CHECK-T16-LABEL: func2:
+; CHECK-T16: @ %bb.0:
+; CHECK-T16-NEXT: .save {r4, lr}
+; CHECK-T16-NEXT: push {r4, lr}
+; CHECK-T16-NEXT: mov r4, r1
+; CHECK-T16-NEXT: eors r1, r3
+; CHECK-T16-NEXT: adds r2, r0, r2
+; CHECK-T16-NEXT: adcs r3, r4
+; CHECK-T16-NEXT: eors r4, r3
+; CHECK-T16-NEXT: bics r4, r1
+; CHECK-T16-NEXT: asrs r1, r3, #31
+; CHECK-T16-NEXT: cmp r4, #0
+; CHECK-T16-NEXT: mov r0, r1
+; CHECK-T16-NEXT: bmi .LBB1_2
+; CHECK-T16-NEXT: @ %bb.1:
+; CHECK-T16-NEXT: mov r0, r2
+; CHECK-T16-NEXT: .LBB1_2:
+; CHECK-T16-NEXT: cmp r4, #0
+; CHECK-T16-NEXT: bmi .LBB1_4
+; CHECK-T16-NEXT: @ %bb.3:
+; CHECK-T16-NEXT: mov r1, r3
+; CHECK-T16-NEXT: pop {r4, pc}
+; CHECK-T16-NEXT: .LBB1_4:
+; CHECK-T16-NEXT: movs r2, #1
+; CHECK-T16-NEXT: lsls r2, r2, #31
+; CHECK-T16-NEXT: eors r1, r2
+; CHECK-T16-NEXT: pop {r4, pc}
;
; CHECK-T2-LABEL: func2:
; CHECK-T2: @ %bb.0:
@@ -115,6 +117,35 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-ARM-NEXT: eormi r2, r1, r2, asr #31
; CHECK-ARM-NEXT: mov r1, r2
; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T15TE-LABEL: func2:
+; CHECK-T15TE: @ %bb.0:
+; CHECK-T15TE-NEXT: .save {r4, lr}
+; CHECK-T15TE-NEXT: push {r4, lr}
+; CHECK-T15TE-NEXT: movs r4, r1
+; CHECK-T15TE-NEXT: eors r1, r3
+; CHECK-T15TE-NEXT: adds r2, r0, r2
+; CHECK-T15TE-NEXT: adcs r3, r4
+; CHECK-T15TE-NEXT: eors r4, r3
+; CHECK-T15TE-NEXT: bics r4, r1
+; CHECK-T15TE-NEXT: asrs r1, r3, #31
+; CHECK-T15TE-NEXT: cmp r4, #0
+; CHECK-T15TE-NEXT: push {r1}
+; CHECK-T15TE-NEXT: pop {r0}
+; CHECK-T15TE-NEXT: bmi .LBB1_2
+; CHECK-T15TE-NEXT: @ %bb.1:
+; CHECK-T15TE-NEXT: movs r0, r2
+; CHECK-T15TE-NEXT: .LBB1_2:
+; CHECK-T15TE-NEXT: cmp r4, #0
+; CHECK-T15TE-NEXT: bmi .LBB1_4
+; CHECK-T15TE-NEXT: @ %bb.3:
+; CHECK-T15TE-NEXT: movs r1, r3
+; CHECK-T15TE-NEXT: pop {r4, pc}
+; CHECK-T15TE-NEXT: .LBB1_4:
+; CHECK-T15TE-NEXT: movs r2, #1
+; CHECK-T15TE-NEXT: lsls r2, r2, #31
+; CHECK-T15TE-NEXT: eors r1, r2
+; CHECK-T15TE-NEXT: pop {r4, pc}
%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y)
ret i64 %tmp
}
@@ -127,13 +158,13 @@ define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
; CHECK-T1-NEXT: cmp r0, r1
; CHECK-T1-NEXT: blt .LBB2_2
; CHECK-T1-NEXT: @ %bb.1:
-; CHECK-T1-NEXT: mov r0, r1
+; CHECK-T1-NEXT: {{movs|mov}} r0, r1
; CHECK-T1-NEXT: .LBB2_2:
; CHECK-T1-NEXT: ldr r1, .LCPI2_1
; CHECK-T1-NEXT: cmp r0, r1
; CHECK-T1-NEXT: bgt .LBB2_4
; CHECK-T1-NEXT: @ %bb.3:
-; CHECK-T1-NEXT: mov r0, r1
+; CHECK-T1-NEXT: {{movs|mov}} r0, r1
; CHECK-T1-NEXT: .LBB2_4:
; CHECK-T1-NEXT: bx lr
; CHECK-T1-NEXT: .p2align 2
@@ -196,13 +227,13 @@ define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
; CHECK-T1-NEXT: cmp r0, #127
; CHECK-T1-NEXT: blt .LBB3_2
; CHECK-T1-NEXT: @ %bb.1:
-; CHECK-T1-NEXT: mov r0, r1
+; CHECK-T1-NEXT: {{movs|mov}} r0, r1
; CHECK-T1-NEXT: .LBB3_2:
; CHECK-T1-NEXT: mvns r1, r1
; CHECK-T1-NEXT: cmp r0, r1
; CHECK-T1-NEXT: bgt .LBB3_4
; CHECK-T1-NEXT: @ %bb.3:
-; CHECK-T1-NEXT: mov r0, r1
+; CHECK-T1-NEXT: {{movs|mov}} r0, r1
; CHECK-T1-NEXT: .LBB3_4:
; CHECK-T1-NEXT: bx lr
;
@@ -252,13 +283,13 @@ define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
; CHECK-T1-NEXT: cmp r0, #7
; CHECK-T1-NEXT: blt .LBB4_2
; CHECK-T1-NEXT: @ %bb.1:
-; CHECK-T1-NEXT: mov r0, r1
+; CHECK-T1-NEXT: {{movs|mov}} r0, r1
; CHECK-T1-NEXT: .LBB4_2:
; CHECK-T1-NEXT: mvns r1, r1
; CHECK-T1-NEXT: cmp r0, r1
; CHECK-T1-NEXT: bgt .LBB4_4
; CHECK-T1-NEXT: @ %bb.3:
-; CHECK-T1-NEXT: mov r0, r1
+; CHECK-T1-NEXT: {{movs|mov}} r0, r1
; CHECK-T1-NEXT: .LBB4_4:
; CHECK-T1-NEXT: bx lr
;
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